Eric Beyne

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 33

Top Topics

Integrated Circuit

Solder Ball Connect

Top Venues

Microelectron. Reliab.

VLSI Technology and Circuits

Publications

Mohamed Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, Giuliano Sisto, Moritz Brunion, Rongmei Chen, Geert Van der Plas, Eric Beyne, Dragomir Milojevic
Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. 3DIC (2023)
Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic
Impact of gate-level clustering on automated system partitioning of 3D-ICs. CoRR (2023)
Quentin Delhaye, Eric Beyne, Joël Goossens, Geert Van der Plas, Dragomir Milojevic
Impact of gate-level clustering on automated system partitioning of 3D-ICs. Microelectron. J. 139 (2023)
Eric Beyne, Anne Jourdain, Gerald Beyer
Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). VLSI Technology and Circuits (2023)
Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty
IP Session on Chiplet: Design, Assembly, and Test. VTS (2023)
Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE (2023)
Anabela Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits (2022)
Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. SLIP (2022)
Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. IEEE Trans. Very Large Scale Integr. Syst. 30 (5) (2022)
Lin Hou, Emmanuel Chery, Kristof Croes, Davide Tierno, Soon Aik Chew, Yangyin Chen, Peter Rakbin, Eric Beyne
Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism. IRPS (2022)
R. Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, A. Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits (2022)
Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne
Efficient Backside Power Delivery for High-Performance Computing Systems. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
M. Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, N. Pinho, Tomas Webers, Dimitrios Velenis, A. Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke
(Why do we need) Wireless Heterogeneous Integration (anyway?). VLSI Technology and Circuits (2022)
K. Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, J. De Boeck, Guido Groeseneken, Julien Ryckaert, Gert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits (2022)
Geert Van der Plas, Eric Beyne
Design and Technology Solutions for 3D Integrated High Performance Systems. VLSI Circuits (2021)
Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). SLIP (2021)
Kristof J. P. Jacobs, Michele Stucchi, Eric Beyne
Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy. IEEE Trans. Instrum. Meas. 70 (2021)
Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC (2019)
Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 3DIC (2019)
Fumihiro Inoue, Julien Bertheau, Samuel Suhard, Alain Phommahaxay, Takuya Ohashi, Tetsuro Kinoshita, Yohei Kinoshita, Eric Beyne
Protective Layer for Collective Die to Wafer Hybrid Bonding. 3DIC (2019)
Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne
A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express 15 (13) (2018)
Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne, Kristof Croes
TSV process-induced MOS reliability degradation. IRPS (2018)
Melina Lofrano, Vladimir Cherman, Mario Gonzalez, Eric Beyne
Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly. Microelectron. Reliab. 87 (2018)
Kristof Croes, Vladimir Cherman, Melina Lofrano, Houman Zahedmanesh, Luka Kljucar, Mario Gonzalez, Ingrid De Wolf, Zsolt Tokei, Eric Beyne
Stress mitigation of 3D-stacking/packaging induced stresses. IRPS (2018)
Kristof J. P. Jacobs, T. Wang, Michele Stucchi, Mario Gonzalez, Kris Croes, Ingrid De Wolf, Eric Beyne
Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices. Microelectron. Reliab. (2017)
Luka Kljucar, Mario Gonzalez, Kristof Croes, Ingrid De Wolf, Joke De Messemaeker, Gayle Murdoch, Philip Nolmans, Joeri De Vos, Jürgen Bömmels, Eric Beyne, Zsolt Tokei
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects. Microelectron. Reliab. 79 (2017)
Jaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey, Geraldine Jamieson, Fumihiro Inoue, Tomas Webers, Pieter Bex, Giovanni Capuz, Eric Beyne, John Slabbekoorn, Teng Wang, Anne Jourdain, Gerald Beyer, Kenneth June Rebibis, Andy Miller
Die to wafer 3D stacking for below 10um pitch microbumps. 3DIC (2016)
Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne, Mohand Brouri, Praveen Nalla, Sanjay Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu
Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. 3DIC (2016)
C. Roda Neve, Mikael Detalle, Philip Nolmans, Yunlong Li, Joeri De Vos, Geert Van der Plas, Gerald Beyer, Eric Beyne
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. 3DIC (2016)
Joeri De Vos, Lan Peng, Alain Phommahaxay, Joost Van Ongeval, Andy Miller, Eric Beyne, Florian Kurz, Thomas Wagenleiter, Markus Wimplinger, Thomas Uhrmann
Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects. 3DIC (2016)
Kristof Croes, Joke De Messemaeker, Yunlong Li, Wei Guo, Olalla Varela Pedreira, Vladimir Cherman, Michele Stucchi, Ingrid De Wolf, Eric Beyne
Reliability Challenges Related to TSV Integration and 3-D Stacking. IEEE Des. Test 33 (3) (2016)
Eric Beyne
The 3-D Interconnect Technology Landscape. IEEE Des. Test 33 (3) (2016)
Anne Jourdain, Joeri De Vos, Fumihiro Inoue, Kenneth J. Rebibis, Andy Miller, Gerald Beyer, Eric Beyne, Edward Walsby, Jash Patel, Oliver Ansell, Janet Hopkins, Huma Ashraf, Dave Thomas
Extreme wafer thinning optimization for via-last applications. 3DIC (2016)
A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, M. Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Philippe P. Absil
Through silicon via to FinFET noise coupling in 3-D integrated circuits. ICICDT (2015)
Herman Oprins, Vladimir Cherman, Geert Van der Plas, F. L. T. Maggioni, Joeri De Vos, Eric Beyne
Thermal experimental and modeling analysis of high power 3D packages. ICICDT (2015)
Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne
Processing active devices on Si interposer and impact on cost. 3DIC (2015)
Nabi Nabiollahi, Nele Moelans, Mario Gonzalez, Joke De Messemaeker, Christopher J. Wilson, Kristof Croes, Eric Beyne, Ingrid De Wolf
Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling. Microelectron. Reliab. 55 (5) (2015)
Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean
Active-lite interposer for 2.5 & 3D integration. VLSIC (2015)
Soon-Wook Kim, Lan Peng, Andy Miller, Gerald Beyer, Eric Beyne, Chung-Sun Lee
Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics. 3DIC (2015)
Joke De Messemaeker, O. Varela Pedreira, A. Moussa, Nabi Nabiollahi, Kris Vanstreels, Stefaan Van Huylenbroeck, Harold Philipsen, Patrick Verdonck, Bart Vandevelde, Ingrid De Wolf, Eric Beyne, Kris Croes
Impact of oxide liner properties on TSV Cu pumping and TSV stress. IRPS (2015)
Eric Beyne
3D system integration research at IMEC. 3DIC (2015)
Bart Vandevelde, Andrej Ivankovic, B. Debecker, Melina Lofrano, Kris Vanstreels, Wei Guo, Vladimir Cherman, Marcel Gonzalez, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Zsolt Tokei
Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling. Microelectron. Reliab. 54 (6-7) (2014)
Yunlong Li, Stefaan Van Huylenbroeck, Els Van Besien, Xiaoping Shi, Chen Wu, Michele Stucchi, Gerald Beyer, Eric Beyne, Ingrid De Wolf, Kristof Croes
Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. Microelectron. Reliab. 54 (9-10) (2014)
Prashant Agrawal, Dragomir Milojevic, Praveen Raghavan, Francky Catthoor, Liesbet Van der Perre, Eric Beyne, Ravi Varadarajan
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform. IEEE Embed. Syst. Lett. 6 (4) (2014)
X. Sun, Geert Van der Plas, Mikael Detalle, Eric Beyne
Analysis of 3D interconnect performance: Effect of the Si substrate resistivity. 3DIC (2014)
Joeri De Vos, Vladimir Cherman, Mikael Detalle, Teng Wang, Abdellah Salahouelhadj, Robert Daily, Geert Van der Plas, Eric Beyne
Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges. 3DIC (2014)
F. L. T. Maggioni, Herman Oprins, Eric Beyne, Ingrid De Wolf, Martine Baelmans
Fast convolution based thermal model for 3D-ICs: Methodology, accuracy analysis and package impact. Microelectron. J. 45 (12) (2014)
Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne
Design issues in heterogeneous 3D/2.5D integration. ASP-DAC (2013)
Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne
Si interposer build-up options and impact on 3D system cost. 3DIC (2013)
Wei Guo, Geert Van der Plas, Andrej Ivankovic, Geert Eneman, Vladimir Cherman, Bart De Wachter, Abdelkarim Mercha, Mario Gonzalez, Yann Civale, Augusto Redolfi, Thibault Buisson, A. Jourdan, Bart Vandevelde, Kenneth J. Rebibis, Ingrid De Wolf, Antonio La Manna, Gerald Beyer, Eric Beyne, Bart Swinnen
3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. ICICDT (2012)
Ingrid De Wolf, Kris Croes, O. Varela Pedreira, Riet Labie, Augusto Redolfi, M. Van De Peer, Kris Vanstreels, C. Okoro, Bart Vandevelde, Eric Beyne
Cu pumping in TSVs: Effect of pre-CMP thermal budget. Microelectron. Reliab. 51 (9-11) (2011)
Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46 (1) (2011)
Eric Beyne, Pol Marchal, Geert Van der Plas
3D heterogeneous system integration: application driver for 3D technology development. DAC (2011)
Y. H. Hu, C. S. Liu, M. J. Lii, Kenneth J. Rebibis, Anne Jourdain, Antonio La Manna, Gerald Beyer, Eric Beyne, C. H. Yu
3D stacking using Cu-Cu direct bonding. 3DIC (2011)
Antonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, Kenneth J. Rebibis, W. Zhang, Eric Beyne
3D stacking using ultra thin dies. 3DIC (2011)
Eric Beyne
Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions. 3DIC (2011)
Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne
In-tier diagnosis of power domains in 3D TSV ICs. 3DIC (2011)
Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. DATE (2011)
Alain Phommahaxay, Anne Jourdain, Greet Verbinnen, Tobias Woitke, Peter Bisson, Markus Gabriel, Walter Spiess, Alice Guerrero, Jeremy McCutcheon, Rama Puligadda, Pieter Bex, Axel Van den Eede, Bart Swinnen, Gerald Beyer, Andy Miller, Eric Beyne
Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding. 3DIC (2011)
Andrej Ivankovic, Geert Van der Plas, V. Moroz, M. Choi, Vladimir Cherman, Abdelkarim Mercha, Paul Marchal, Marcel Gonzalez, Geert Eneman, W. Zhang, Thibault Buisson, Mikael Detalle, Antonio La Manna, Diederik Verkest, Gerald Beyer, Eric Beyne, Bart Vandevelde, Ingrid De Wolf, Dirk Vandepitte
Analysis of microbump induced stress effects in 3D stacked IC technologies. 3DIC (2011)
Sandip Halder, Ingrid De Wolf, Alain Phommahaxay, Andy Miller, Mireille Maenhoudt, Gerald Beyer, Bart Swinnen, Eric Beyne
In-line metrology and inspection for process control during 3D stacking of IC's. 3DIC (2011)
Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne
Cost effectiveness of 3D integration options. 3DIC (2010)
Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. CICC (2010)
Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne, Youssef Travaly, Bart Swinnen
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. 3DIC (2010)
Yann Civale, Marcel Gonzalez, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne
A novel concept for ultra-low capacitance via-last TSV. 3DIC (2010)
Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne
Design issues and considerations for low-cost 3D TSV IC technology. ISSCC (2010)
Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne
Impact of 3D design choices on manufacturing cost. 3DIC (2009)
Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne, Bart Swinnen
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). 3DIC (2009)
Yann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen, P. Jaenen, Rahul Agarwal, F. Duval, Philippe Soussan, Youssef Travaly, Eric Beyne
Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. 3DIC (2009)
Paul Marchal, Bruno Bougard, Guruprasad Katti, Michele Stucchi, Wim Dehaene, Antonis Papanikolaou, Diederik Verkest, Bart Swinnen, Eric Beyne
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot. Proc. IEEE 97 (1) (2009)
Eric Beyne
Tutorial T7A: Advanced IC Packaging. VLSI Design (2007)
Bart Vandevelde, Mario Gonzalez, Paresh Limaye, Petar Ratchev, Eric Beyne
Thermal cycling reliability of SnAgCu and SnPb solder joints: A comparison for several IC-packages. Microelectron. Reliab. 47 (2-3) (2007)
J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne
Constant impedance scaling paradigm for interconnect synthesis. SLIP (2006)
J. Balachandran, Maarten Kuijk, Steven Brebels, Geert Carchon, Walter De Raedt, Bart Nauwelaers, Eric Beyne
Efficient Link Architecture for On-Chip Serial links and Networks. SoC (2006)
Kris Baert, Bert Gyselinckx, Tom Torfs, Vladimir Leonov, Refet Firat Yazicioglu, Steven Brebels, Stéphane Donnay, J. Vanfletern, M. Pastreen, Eric Beyne, Chris Van Hoof
Technologies for highly miniaturized autonomous sensor networks. Microelectron. J. 37 (12) (2006)
J. Balachandran, Steven Brebels, Geert Carchon, Walter De Raedt, Eric Beyne, Maarten Kuijk, Bart Nauwelaers
Constant Impedance Scaling Paradigm for Scaling LC transmission lines. ISQED (2006)
J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne
Wafer-level package interconnect options. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne
Analysis and modeling of power grid transmission lines. DATE (2006)
Mathieu Vanden Bulcke, Kris Baert, Eric Beyne, Mario Gonzalez, Christophe Winters, Tomas Webers
Active Electrode Arrays by Chip Embedding in a Flexible Silicone Carrier. EMBC (2006)
J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne
Package level interconnect options. SLIP (2005)
Marcel Gonzalez, Bart Vandevelde, R. Van Hoof, Eric Beyne
Characterization and FE analysis on the shear test of electronic materials. Microelectron. Reliab. 44 (12) (2004)
Philippe Soussan, G. Lekens, R. Dreesen, Ward De Ceuninck, Eric Beyne
Advantage of In-situ over Ex-situ techniques as reliability tool: Aging kinetics of Imec's MCM-D discrete passives devices. Microelectron. Reliab. 43 (9-11) (2003)
Arun Chandrasekhar, Steven Brebels, Serguei Stoukatch, Eric Beyne, Walter De Raedt, Bart Nauwelaers
The influence of packaging materials on RF performance. Microelectron. Reliab. 43 (3) (2003)
Hong Meng Ho, Wai Lam, Serguei Stoukatch, Petar Ratchev, Charles J. Vath, Eric Beyne
Direct gold and copper wires bonding on copper. Microelectron. Reliab. 43 (6) (2003)
Bart Vandevelde, Dominiek Degryse, Eric Beyne, Eric Roose, Dorina Corlatan, Guido Swaelen, Geert Willems, Filip Christiaens, Alcatel Bell, Dirk Vandepitte
Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages. Microelectron. Reliab. 43 (2) (2003)
Stéphane Donnay, Philip Pieters, Kristof Vaesen, Wim Diels, Piet Wambacq, Walter De Raedt, Eric Beyne, Marc Engels, Ivo Bolsens
Chip-package codesign of a low-power 5-GHz RF front end. Proc. IEEE 88 (10) (2000)
Claudio Truzzi, Eric Beyne, Edwin Ringoot
Design of Test Modules for the Analysis of MCM Interconnects. ED&TC (1996)
Claudio Truzzi, Eric Beyne, Edwin Ringoot, J. Peeters
Signal propagation in high-speed MCM circuits. ICCD (1995)