Makoto Nagata

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 64

Top Venues

IEICE Trans. Electron.

ISSCC

IEEE J. Solid State Circuits

IEICE Electron. Express

Publications

Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata
On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection. COSADE (2024)
Henian Li, Lang Lin, Norman Chang, Sreeja Chowdhury, Dylan Mcguire, Bozidar Novakovic, Kazuki Monta, Makoto Nagata, Ying-Shiun Li, Pramod M. S, Piin-Chen Yeh, J.-S. Roger Jang, Chengjie Xi, Qiutong Jin, Navid Asadi, Mark M. Tehranipoor
Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation. HOST (2024)
Koh Watanabe, Ryota Sakai, Satoshi Tanaka, Makoto Nagata, Hideki Osaka, Atsushi Nakamura, Ifong Wu, Yasushi Matsumoto, Kaoru Gotoh
Electromagnetic Interference With the Mobile Communication Devices in Unmanned Aerial Vehicles and Its Countermeasures. IEEE Access 12 (2024)
Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
A Triturated Sensing System. ISSCC (2023)
Makoto Nagata, Massimo Alioto
Guest Editorial IEEE 2022 European Solid-State Circuits Conference. IEEE J. Solid State Circuits 58 (7) (2023)
Ryozo Takahashi, Takuji Miki, Makoto Nagata
An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique. IEICE Trans. Electron. 106 (10) (2023)
Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata
Characterization of Backside ESD Impacts on Integrated Circuits. IRPS (2023)
Kazuki Monta, Makoto Nagata, Josep Balasch, Ingrid Verbauwhede
On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits. DAC (2023)
Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki, Makoto Nagata
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. IEICE Trans. Electron. 106 (10) (2023)
Kazuki Monta, Lang Lin, Jimin Wen, Harsh Shrivastav, Calvin Chow, Hua Chen, Joao Geada, Sreeja Chowdhury, Nitin Pundir, Norman Chang, Makoto Nagata
Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis. ACM J. Emerg. Technol. Comput. Syst. 19 (1) (2023)
Tom Kocmi, Eleftherios Avramidis, Rachel Bawden, Ondrej Bojar, Anton Dvorkovich, Christian Federmann, Mark Fishel, Markus Freitag, Thamme Gowda, Roman Grundkiewicz, Barry Haddow, Philipp Koehn, Benjamin Marie, Christof Monz, Makoto Morishita, Kenton Murray, Makoto Nagata, Toshiaki Nakazawa, Martin Popel, Maja Popovic, Mariya Shmatova
Findings of the 2023 Conference on Machine Translation (WMT23): LLMs Are Here but Not Quite There Yet. WMT (2023)
Makoto Nagata
Design of Circuits and Packaging Systems for Security Chips. IEICE Trans. Electron. 106 (7) (2023)
Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Takuji Miki, Makoto Nagata, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo
Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. IRPS (2022)
Makoto Nagata
Exploring Fault Injection Attack Resilience of Secure IC Chips : Invited Paper. IRPS (2022)
Makoto Nagata, Takuji Miki, Noriyuki Miura
Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. 30 (1) (2022)
Takuji Miki, Ryozo Takahashi, Makoto Nagata
charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays. IEICE Electron. Express 19 (8) (2022)
Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test 39 (5) (2022)
Makoto Nagata
Foreword. IEICE Trans. Electron. (7) (2021)
Lang Lin, Deqi Zhu, Jimin Wen, Hua Chen, Yu Lu, Norman Chang, Calvin Chow, Harsh Shrivastav, Chia-Wei Chen, Kazuki Monta, Makoto Nagata
Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification. HOST (2021)
Makoto Nagata
Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited). SLIP (2021)
Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. ETS (2021)
Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Shoei Nashimoto, Daisuke Suzuki, Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. J. Cryptogr. Eng. 11 (3) (2021)
Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18 (9) (2021)
Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs (1) (2020)
Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69 (4) (2020)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55 (10) (2020)
Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. (10) (2020)
Makoto Nagata
Foreword. IEICE Trans. Electron. (4) (2020)
Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS (2020)
Lang Lin, Dinesh Selvakumaran, Deqi Zhu, Norman Chang, Calvin Chow, Makoto Nagata, Kazuki Monta
Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis. iSES (2020)
Makoto Nagata
Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security - Invited Paper. SPACE (2019)
Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, Shoei Nashimoto, Daisuke Suzuki
A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. ASHES@CCS (2019)
Takuji Miki, Noriyuki Miura, Makoto Nagata
Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. IEICE Trans. Electron. (7) (2019)
Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC (2019)
Makoto Nagata
On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper. ASICON (2019)
Makoto Nagata, Takuji Miki, Noriyuki Miura
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC (2019)
Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
Side-channel leakage from sensor-based countermeasures against fault injection attack. Microelectron. J. 90 (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC (2019)
Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne
A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express 15 (13) (2018)
Naveen Verma, Fatih Hamzaoglu, Makoto Nagata, Leland Chang
Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees. ISSCC (2018)
Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor. IEEE J. Solid State Circuits 53 (11) (2018)
Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD (2018)
Patrick P. Mercier, Long Yan, Makoto Nagata
Session 17 overview: Technologies for health and society: Technology directions subcommittee. ISSCC (2018)
Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. IEEE J. Solid State Circuits 53 (10) (2018)
Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack. ISSCC (2018)
Shinichiro Shiratake, Edoardo Charbon, Leland Chang, Makoto Nagata
Session 30 overview: Emerging memories: Memory and technology directions subcommittees. ISSCC (2018)
Jan Genoe, Frederic Gianesello, Makoto Nagata
Session 21 overview: Extending silicon and its applications: Technology directions subcommittee. ISSCC (2018)
Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. A-SSCC (2017)
Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. (6) (2017)
Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
An FPGA-compatible PLL-based sensor against fault injection attack. ASP-DAC (2017)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. 30 (2) (2017)
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama
Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express 14 (2) (2017)
Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. FDTC (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata
x-point multi-layer metal nano-dot structure. ISSCC (2017)
Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). IACR Cryptol. ePrint Arch. 2016 (2016)
Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger
PLL to the rescue: a novel EM fault countermeasure. DAC (2016)
Kohei Matsuda, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Tatsuya Fujii, Kazuo Sakiyama
On-chip substrate-bounce monitoring for laser-fault countermeasure. AsianHOST (2016)
Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata
F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC (2016)
Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC (2016)
Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. FDTC (2016)
Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC (2015)
Satoshi Tanaka, Peng Fan, Jingyan Ma, Hanae Aoki, Masahiro Yamaguchi, Makoto Nagata, Sho Muroga
Analysis of on-chip digital noise coupling path for wireless communication IC test chip. EMC Compo (2015)
Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda
In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking. IEEE Des. Test 32 (6) (2015)
Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50 (11) (2015)
Hiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata
Nano-Function materials for TSV technologies. 3DIC (2015)
Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC (2015)
Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki
EM attack sensor: concept, circuit, and design-automation methodology. DAC (2015)
Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Shuichi Ohno, Yuji Wakasa, Makoto Nagata
Optimal error feedback filters for uniform quantizers at remote sensors. ICASSP (2015)
Kohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata
At-Product-Test Dedicated Adaptive supply-resonance suppression. VTS (2015)
Makoto Nagata, Stefano Stanzione
Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee. ISSCC (2015)
Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. VLSI-DAT (2014)
Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata
Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking. IEICE Trans. Electron. (6) (2014)
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. (4) (2014)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES (2014)
Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger
Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST (2014)
Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 49 (12) (2014)
Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans. Electron. (6) (2014)
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. (4) (2014)
Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS (2014)
Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. 2014 (2014)
Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata
AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model. IEICE Trans. Electron. (4) (2014)
Takefumi Yoshikawa, Makoto Nagata
Timing margin enhancement technique for current mode interface. IEICE Electron. Express 11 (19) (2014)
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED (2014)
Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC (2014)
Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC (2014)
Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE (2014)
Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC (2014)
Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata
Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits. IEICE Trans. Electron. (4) (2013)
Naoya Azuma, Makoto Nagata
Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components. IEICE Trans. Electron. (6) (2013)
Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata
Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Satoshi Takaya, Makoto Nagata, Atsushi Sakai, Takashi Kariya, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. ISSCC (2013)
Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. EMC Compo (2013)
Makoto Nagata, Shunsuke Shimazaki, Naoya Azuma, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Satoshi Tanaka, Masahiro Yamaguchi
Measurement-based diagnosis of wireless communication performance in the presence of in-band interferers in RF ICs. EMC Compo (2013)
Satoshi Takaya, Makoto Nagata, Hiroaki Ikeda
Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs. 3DIC (2013)

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Makoto Nagata