Ioannis Savidis

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 73

Top Topics

Subgraph Isomorphism

State Transitions

Analog Circuits

Top Venues

ACM Great Lakes Symposium on VLSI

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Pratik Shrestha, Ioannis Savidis
EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation. ISQED (2024)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
DNA: DC Nodal Analysis Attack for Analog Circuits. ISCAS (2024)
Zhengfeng Wu, Ioannis Savidis
Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits. ISCAS (2024)
Zhengfeng Wu, Ioannis Savidis
Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling. ISQED (2024)
Alec Aversa, Ioannis Savidis
Harnessing Heterogeneity for Targeted Attacks on 3-D ICs. ACM Great Lakes Symposium on VLSI (2024)
Pratik Shrestha, Alec Aversa, Saran Phatharodom, Ioannis Savidis
EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation. ACM Great Lakes Symposium on VLSI (2024)
Ziyi Chen, Ioannis Savidis
Block Configuration Algorithms for a Reconfigurable Analog Array. ISCAS (2024)
Ziyi Chen, Ioannis Savidis
A Power Side-Channel Attack on Flash ADC. ISCAS (2023)
Pratik Shrestha, Ioannis Savidis
Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect. ISCAS (2023)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
Hidden Costs of Analog Deobfuscation Attacks. IEEE Trans. Very Large Scale Integr. Syst. 31 (11) (2023)
Zhengfeng Wu, Isabel Song, Ioannis Savidis
Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation. MLCAD (2023)
Zhengfeng Wu, Ioannis Savidis
Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies. ISCAS (2023)
Zhengfeng Wu, Ioannis Savidis
Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks. MLCAD (2022)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
Practical Performance of Analog Attack Techniques. HOST (2022)
Ziyi Chen, Ioannis Savidis
Reconfigurable Analog Array for Hardware Security. ISCAS (2022)
Vaibhav Venugopal Rao, Avesta Sasan, Ioannis Savidis
Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits. ISQED (2022)
Tanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Seyed Aresh Beheshti Shirazi, Ali Mirzaeian, Xiaojie Guo, Sai Manoj P. D., Houman Homayoun, Ioannis Savidis, Liang Zhao, Avesta Sasan
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis. ACM Great Lakes Symposium on VLSI (2022)
Pratik Shrestha, Saran Phatharodom, Ioannis Savidis
Graph Representation Learning for Gate Arrival Time Prediction. MLCAD (2022)
Pratik Shrestha, Ioannis Savidis
Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking. ISCAS (2022)
Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan
Adaptive-Gravity: A Defense Against Adversarial Samples. ISQED (2022)
Zhengfeng Wu, Ioannis Savidis
Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes. ISCAS (2022)
Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan
Adaptive-Gravity: A Defense Against Adversarial Samples. CoRR (2022)
Md Shazzad Hossain, Ioannis Savidis
Energy Efficient Computing with Heterogeneous DNN Accelerators. AICAS (2021)
Kyle Juretus, Ioannis Savidis
Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (1) (2021)
Md Shazzad Hossain, Ioannis Savidis
Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (4) (2021)
Ziyi Chen, Ioannis Savidis
Reconfigurable Array for Analog Applications. ICCD (2021)
Zhengfeng Wu, Ioannis Savidis
Variation-aware Analog Circuit Sizing with Classifier Chains. MLCAD (2021)
Kyle Juretus, Ioannis Savidis
Synthesis of Hidden State Transitions for Sequential Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (1) (2021)
Vaibhav Venugopal Rao, Ioannis Savidis
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29 (12) (2021)
Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj, Ioannis Savidis, Houman Homayoun, Avesta Sasan
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop. ACM Great Lakes Symposium on VLSI (2021)
Saran Phatharodom, Avesta Sasan, Ioannis Savidis
SAT-attack Resilience Measure for Access Restricted Circuits. ACM Great Lakes Symposium on VLSI (2021)
Kyle Juretus, Ioannis Savidis
Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (8) (2020)
Md Shazzad Hossain, Ioannis Savidis
Dynamic idle core management and leakage current reuse in MPSoC platforms. ISLPED (2020)
Zhengfeng Wu, Ioannis Savidis
CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing. MLCAD (2020)
Kyle Juretus, Ioannis Savidis
Reducing Logic Locking Key Leakage through the Scan Chain. ISCAS (2020)
Marko Jacovic, Kyle Juretus, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
Physical Layer Encryption for Wireless OFDM Communication Systems. J. Hardw. Syst. Secur. 4 (3) (2020)
Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis
Security Vulnerabilities of Obfuscated Analog Circuits. ISCAS (2020)
Saran Phatharodom, Nagarajan Kandasamy, Ioannis Savidis
Modeling SAT-Attack Search Complexity. ISCAS (2020)
Md Shazzad Hossain, Ioannis Savidis
Recycling of unused leakage current for energy efficient multi-voltage systems. Microelectron. J. 101 (2020)
Md Shazzad Hossain, Ioannis Savidis
Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing. Microelectron. J. 102 (2020)
Divya Pathak, Ioannis Savidis
Applying Swarm Intelligence to Distributed On-Chip Power Management. ICCD (2019)
Md Shazzad Hossain, Ioannis Savidis
Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems. ISCAS (2019)
Kyle Juretus, Ioannis Savidis
Increasing the SAT Attack Resiliency of In-Cone Logic Locking. ISCAS (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
Securing Wireless Communication via Hardware-Based Packet Obfuscation. J. Hardw. Syst. Secur. 3 (3) (2019)
Vaibhav Venugopal Rao, Ioannis Savidis
Mesh Based Obfuscation of Analog Circuit Properties. ISCAS (2019)
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis
Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED (2019)
Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis
Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. ACM Great Lakes Symposium on VLSI (2019)
Kyle Juretus, Ioannis Savidis
Time Domain Sequential Locking for Increased Security. ISCAS (2018)
Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead
Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. ICCD (2018)
Md Shazzad Hossain, Ioannis Savidis
Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery. IGSC (2018)
Hossein Sayadi, Divya Pathak, Ioannis Savidis, Houman Homayoun
Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning. ASP-DAC (2018)
Ioannis Savidis, Swarup Bhunia, Gang Qu, Matthew J. Casto, Jeremy Muldavin
Securing the Systems of the Future - Techniques for a Shifting Attack Space. ACM Great Lakes Symposium on VLSI (2018)
Divya Pathak, Ioannis Savidis
On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Vaibhav Venugopal Rao, Ioannis Savidis
Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory. APCCAS (2018)
Kyle Juretus, Ioannis Savidis
Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security. APCCAS (2018)
Md Shazzad Hossain, Ioannis Savidis
Noise Constrained Optimum Selection of Supply Voltage for IoT Applications. ISCAS (2018)
Isuru Daulagala, Ioannis Savidis
Clock tree synthesis for heterogeneous 3-D integrated circuits. SLIP (2017)
Divya Pathak, Houman Homayoun, Ioannis Savidis
Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery. ACM Great Lakes Symposium on VLSI (2017)
Vaibhav Venugopal Rao, Ioannis Savidis
Protecting analog circuits with parameter biasing obfuscation. LATS (2017)
James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
Physical gate based preamble obfuscation for securing wireless communication. ICNC (2017)
Md Shazzad Hossain, Ioannis Savidis
Bi-directional input/output circuits with integrated level shifters for near-threshold computing. MWSCAS (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Vaibhav Venugopal Rao, Ioannis Savidis
Parameter biasing obfuscation for analog IP protection. HOST (2017)
Divya Pathak, Houman Homayoun, Ioannis Savidis
Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery. IEEE Trans. Very Large Scale Integr. Syst. 25 (9) (2017)
Kyle Juretus, Ioannis Savidis
Reducing logic encryption overhead through gate level key insertion. ISCAS (2016)
Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis
Load Balanced On-Chip Power Delivery for Average Current Demand. ACM Great Lakes Symposium on VLSI (2016)
Kyle Juretus, Ioannis Savidis
Reduced Overhead Gate Level Logic Encryption. ACM Great Lakes Symposium on VLSI (2016)
Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis
Energy efficient on-chip power delivery with run-time voltage regulator clustering. ISCAS (2016)
Md Shazzad Hossain, Ioannis Savidis
Robust near-threshold inverter with improved performance for ultra-low power applications. ISCAS (2016)
Kostas Siozios, Ioannis Savidis, Dimitrios Soudris
A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures. SAMOS (2016)
Ioannis Savidis, Berkehan Ciftcioglu, Jie Xu, Jianyun Hu, Manish Jain, Rebecca Berman, Jing Xue, Peng Liu, Duncan Moore, Gary Wicks, Michael C. Huang, Hui Wu, Eby G. Friedman
Heterogeneous 3-D circuits: Integrating free-space optics with CMOS. Microelectron. J. 50 (2016)
Mohammad Khavari Tavana, Divya Pathak, Mohammad Hossein Hajkazemi, Maria Malik, Ioannis Savidis, Houman Homayoun
Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping. ICCD (2015)
Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun
ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling. DAC (2015)
Ioannis Savidis, Boris Vaisband, Eby G. Friedman
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Divya Pathak, Ioannis Savidis
Run-time voltage detection circuit for 3-D IC power delivery. SoCC (2014)
Boris Vaisband, Ioannis Savidis, Eby G. Friedman
Thermal conduction path analysis in 3-D ICs. ISCAS (2014)
Ioannis Savidis, Selçuk Köse, Eby G. Friedman
Power Noise in TSV-Based 3-D Integrated Circuits. IEEE J. Solid State Circuits 48 (2) (2013)
Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman
Clock Distribution Networks in 3-D Integrated Systems. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Jinhui Wang, Ioannis Savidis, Eby G. Friedman
Thermal analysis of oxide-confined VCSEL arrays. Microelectron. J. 42 (5) (2011)
Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman
Clock distribution models of 3-D integrated systems. ISCAS (2011)
Ioannis Savidis, Syed M. Alam, Ankur Jain, Scott Pozder, Robert E. Jones, Ritwik Chatterjee
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectron. J. 41 (1) (2010)
Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore
An intra-chip free-space optical interconnect. ISCA (2010)
Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman
Clock distribution networks for 3-D ictegrated Circuits. CICC (2008)
Ioannis Savidis, Eby G. Friedman
Electrical modeling and characterization of 3-D vias. ISCAS (2008)