Chulwoo Kim

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 83

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

ISSCC

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min Kim, Ju-Hyung Lee, Young-Chai Ko, Chulwoo Kim
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. IEEE J. Solid State Circuits 59 (6) (2024)
Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. IEEE J. Solid State Circuits 59 (4) (2024)
Junyoung Maeng, Junwon Jeong, Inho Park, Minseob Shim, Chulwoo Kim
A Time-Based Direct MPPT Technique for Low-Power Photovoltaic Energy Harvesting. IEEE Trans. Ind. Electron. 71 (5) (2024)
Hyunjin Kim, ChangHun Park, Inho Park, Taehyeong Park, Seungwoo Park, Chulwoo Kim
A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications. IEEE J. Solid State Circuits 59 (2) (2024)
Taehyeong Park, Hyunjin Kim, Mingi Jeong, Inho Park, Chulwoo Kim
A Fully Integrated Dual-Output Continuously Scalable-Conversion-Ratio SC Converter for Battery-Powered IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (8) (2024)
Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 71 (7) (2024)
Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Junseob So, Seonbeen Lee, Chulwoo Kim
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. IEEE J. Solid State Circuits 59 (8) (2024)
Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (7) (2023)
Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. IEEE J. Solid State Circuits 58 (8) (2023)
Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Inho Park, Jinwoo Jeon, Hyunjin Kim, Taehyeong Park, Junwon Jeong, Chulwoo Kim
A Thermoelectric Energy-Harvesting Interface With Dual-Conversion Reconfigurable DC-DC Converter and Instantaneous Linear Extrapolation MPPT Method. IEEE J. Solid State Circuits 58 (6) (2023)
Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 58 (7) (2023)
Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. ISSCC (2023)
Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 70 (1) (2023)
Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Hyunjin Kim, ChangHun Park, Chulwoo Kim
An Output-Boosted 3-ratio Switched-Capacitor DC-DC Converter with 0.5-to-1.8 V Output Voltage Range for Low-Power IoT Applications. MWSCAS (2022)
Chaegang Lim, Yohan Choi, Jaegeun Song, Soonsung Ahn, Seokwon Jang, Chulwoo Kim
An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 57 (9) (2022)
Jong-Min Kim, Ju-Hyung Lee, Yeongrok Lee, Hong-Seol Cha, Hyunsu Park, Jincheol Sim, Chulwoo Kim, Young-Chai Ko
Experimental Demonstration of RoFSO Transmission Combining WLAN Standard and WDM-FSO over 100m Distance. INFOCOM Workshops (2022)
Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, Chulwoo Kim
A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique. IEEE J. Solid State Circuits 57 (5) (2022)
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. IEEE J. Solid State Circuits 57 (2) (2022)
Jeewan Lee, Yoonjae Choi, Chulwoo Kim
A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers. ISCAS (2022)
Jincheol Sim, Yeonho Lee, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Chulwoo Kim
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Chulwoo Kim
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. ISSCC (2022)
Hyunjin Kim, Taehyeong Park, Chulwoo Kim
A 97.9% Peak Efficiency 9 V Output Three-Switch Hybrid Buck-Boost Power Stage Using 5 V CMOS. MWSCAS (2022)
Junyoung Song, Sewook Hwang, Chulwoo Kim
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 29 (8) (2021)
Hyunjin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Yohan Choi, Chulwoo Kim
A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme. IEEE J. Solid State Circuits 56 (9) (2021)
Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. IEEE Access 9 (2021)
Inho Park, Jinseok Oh, Chulwoo Kim
A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique. ISCAS (2021)
Junyoung Maeng, Inho Park, Minseob Shim, Junwon Jeong, Chulwoo Kim
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications. IEEE J. Solid State Circuits 56 (2) (2021)
Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Chulwoo Kim
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68 (10) (2021)
Hyunjin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Dongju Lim, Chulwoo Kim
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode. IEEE J. Solid State Circuits 56 (3) (2021)
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56 (6) (2021)
Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. IEEE J. Solid State Circuits 56 (2) (2021)
Jinwoo Jeon, Junyoung Maeng, Inho Park, Hyunjin Kim, Chulwoo Kim
A Hybrid DC-DC Converter Capable of Supplying Heavy Load in Step-Up and Step-Down Mode. ISCAS (2021)
Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, Chulwoo Kim
A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector. ISCAS (2021)
Chaegang Lim, Yohan Choi, Yunsoo Park, Jaegeun Song, Soonsung Ahn, Sooho Park, Chulwoo Kim
A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Youngbog Yoon, Chulwoo Kim
An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Junyoung Maeng, Minseob Shim, Junwon Jeong, Inho Park, Yunsoo Park, Chulwoo Kim
A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance. IEEE J. Solid State Circuits 55 (6) (2020)
Youngbog Yoon, Hyunsu Park, Chulwoo Kim
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. IEEE Trans. Circuits Syst. (11) (2020)
Soonsung Ahn, Jaegeun Song, Chaegang Lim, Yohan Choi, Sooho Park, Yunsoo Park, Chulwoo Kim
A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. ISOCC (2020)
Jaehun Jun, Sangsu Lee, Chulwoo Kim
Near threshold voltage digital PLL using low voltage optimised blocks for AR display system. IET Circuits Devices Syst. 14 (2) (2020)
Jaegeun Song, Jaehun Jun, Chulwoo Kim
A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique. IEEE Trans. Circuits Syst. II Express Briefs (7) (2020)
Yunsoo Park, Jaegeun Song, Yohan Choi, Chaegang Lim, Soonsung Ahn, Chulwoo Kim
An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier. IEEE J. Solid State Circuits 55 (9) (2020)
Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim
A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efficiency for Triboelectric Energy-Harvesting Applications. IEEE J. Solid State Circuits 55 (5) (2020)
Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim
A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency. VLSI Circuits (2019)
Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. IEEE J. Solid State Circuits 54 (2) (2019)
Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. ISSCC (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Junwon Jeong, Seokhyeon Jeong, Dennis Sylvester, David T. Blaauw, Chulwoo Kim
A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries. IEEE J. Solid State Circuits 54 (2) (2019)
Junyoung Song, Yongtae Kim, Chulwoo Kim
A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs (12) (2019)
Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. ASP-DAC (2018)
Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghune Park, Chulwoo Kim
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. IEEE Trans. Circuits Syst. II Express Briefs (6) (2018)
Jaehun Jun, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim
A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Jaehun Jun, Jaegeun Song, Chulwoo Kim
A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2018)
Junwon Jeong, Seokhyeon Jeong, Chulwoo Kim, Dennis Sylvester, David T. Blaauw
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries. ASP-DAC (2018)
Yeonho Lee, Yoonjae Choi, Chulwoo Kim
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. ASP-DAC (2018)
Inho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim
A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage. ISSCC (2018)
Wonsup Lee, Baekhee Lee, Xiaopeng Yang, Hayoung Jung, Ilgeun Bok, Chulwoo Kim, Ochae Kwon, Heecheon You
A 3D anthropometric sizing analysis system based on North American CAESAR 3D scan data for design of head wearable products. Comput. Ind. Eng. 117 (2018)
Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Jayoung Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, Chulwoo Kim
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. IEEE Trans. Circuits Syst. II Express Briefs (6) (2017)
Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2017)
Sang-Geun Bae, Yongtae Kim, Yunsoo Park, Chulwoo Kim
3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop. IEEE J. Solid State Circuits 52 (2) (2017)
Jungtaek You, Junyoung Song, Chulwoo Kim
A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM. IEEE Trans. Circuits Syst. II Express Briefs (10) (2017)
Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J. Solid State Circuits 52 (4) (2017)
Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. ISSCC (2017)
Sangsu Lee, Jaehun Jun, Chulwoo Kim
A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. ISOCC (2017)
Chulwoo Kim, Sung-Hyuk Cha, Yoo Jung An, Ned Wilson
On ROC Curve Analysis of Artificial Neural Network Classifiers. FLAIRS Conference (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Young-Jae Min, Chan-Hui Jeong, Junil Moon, Youngsun Han, Soo-Won Kim, Chulwoo Kim
A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system. IEICE Electron. Express 14 (13) (2017)
Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Sang-Geun Bae, Gyungmin Kim, Chulwoo Kim
A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation. IEEE Trans. Circuits Syst. II Express Briefs (10) (2017)
Chulwoo Kim, Martin Brox
Session 18 overview: High-bandwidth DRAM. ISSCC (2016)
Byung Gun Joung, Yangho Seo, Chulwoo Kim
A digital low-dropout(DLDO) regulator with 14dB power supply rejection enhancement. ISOCC (2016)
Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. VLSI Circuits (2016)
Edith Beigné, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 51 (1) (2016)
Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Junyoung Song, Sewook Hwang, Chulwoo Kim
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Yunsoo Park, Jintae Kim, Chulwoo Kim
A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. VLSI Circuits (2016)
Jonathan Chang, Leland Chang, Antoine Dupret, Chulwoo Kim, Fatih Hamzaoglu, Takefumi Yoshikawa
F2: Memory trends: From big data to wearable devices. ISSCC (2015)
Hokyu Lee, Sejin Park, Chaegang Lim, Chulwoo Kim
A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter. IEEE Trans. Circuits Syst. II Express Briefs (4) (2015)
Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim
A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement. IEEE J. Solid State Circuits 50 (2) (2015)
Minseob Shim, Jungmoon Kim, Junwon Jeong, Sejin Park, Chulwoo Kim
Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking Time. IEEE J. Solid State Circuits 50 (10) (2015)
Joon Goo Lee, Seon Wook Kim, Dong-Hyun Kim, Younga Cho, Jae-Sung Rieh, Gyusung Kang, Jongsun Park, Hokyu Lee, Sejin Park, Chulwoo Kim
ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing. Microprocess. Microsystems 39 (8) (2015)
Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. ISSCC (2015)
Chulwoo Kim
Circuit design techniques for multimedia wireline communications. ASICON (2015)
Hokyu Lee, Aurangozeb, Sejin Park, Jintae Kim, Chulwoo Kim
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Hyun-Woo Lee, Chulwoo Kim
Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon
F6: Energy-efficient I/O design for next-generation systems. ISSCC (2014)
Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. ISSCC (2014)
Jungmoon Kim, Minseob Shim, Junwon Jung, Heejun Kim, Chulwoo Kim
A DC-DC boost converter with variation tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applications. ASP-DAC (2014)
Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim
23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement. ISSCC (2014)
Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Heejun Kim, Jungmoon Kim, Minseob Shim, Junwon Jung, Sejin Park, Chulwoo Kim
A digitally controlled DC-DC buck converter with bang-bang control. ICEIC (2014)
Jungmoon Kim, Chulwoo Kim
A single-inductor 8-channel output DC-DC boost converter with time-limited power distribution control and single shared hysteresis comparator. ASP-DAC (2014)

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Chulwoo Kim