Magdy S. Abadir

ORCID

Publication Activity (10 Years)

Years Active: 1983-2019
Publications (10 Years): 3

Top Venues

Publications

Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Magdy S. Abadir, Jayanta Bhadra, Wen Chen, Li-C. Wang
Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification. IEEE Des. Test 34 (5) (2017)
Wen Chen, Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang
Challenges and Trends in Modern SoC Design Verification. IEEE Des. Test 34 (5) (2017)
Li-C. Wang, Magdy S. Abadir
Data Mining In EDA - Basic Principles, Promises, and Constraints. DAC (2014)
Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
Yield optimization using advanced statistical correlation methods. ITC (2014)
Jeff Tikkanen, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
Multivariate outlier modeling for capturing customer returns - How simple it can be. IOLTS (2014)
Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
A pattern mining framework for inter-wafer abnormality analysis. ITC (2013)
Wen Chen, Li-C. Wang, Jayanta Bhadra, Magdy S. Abadir
Novel test analysis to improve structural coverage - A commercial experiment. VLSI-DAT (2013)
Sandip Ray, Jay Bhadra, Magdy S. Abadir, Li-C. Wang
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs. J. Electron. Test. 29 (5) (2013)
Sani R. Nassif, Yale N. Patt, Magdy S. Abadir
Keynote 1 - VLSI 2.0: R&D Post Moore. VLSI-SoC (2013)
Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir
Simulation knowledge extraction and reuse in constrained random processor verification. DAC (2013)
Magdy S. Abadir, Nik Sumikawa, Wen Chen, Li-C. Wang
Data mining based prediction paradigm and its applications in design automation. VLSI-DAT (2012)
Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta
Introduction to special section on verification challenges in the concurrent world. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Nik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir
Screening customer returns with multivariate test analysis. ITC (2012)
Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
An experiment of burn-in time reduction based on parametric test analysis. ITC (2012)
Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir
Novel test detection to improve simulation efficiency - A commercial experiment. ICCAD (2012)
Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir
Understanding customer returns from a test perspective. VTS (2011)
Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir
Forward prediction based on wafer sort data - A case study. ITC (2011)
Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir
Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. DATE (2011)
Alper Sen, Magdy S. Abadir
Coverage metrics for verification of concurrent SystemC designs using mutation testing. HLDVT (2010)
Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch. IEEE Des. Test Comput. 27 (3) (2010)
Magdy S. Abadir
Design for reality: knowledge discovery in design and test data. SBCCI (2010)
Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. DAC (2010)
Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir
Minimizing outlier delay test cost in the presence of systematic variability. ITC (2009)
Amin Khajeh, Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir
TRAM: A tool for Temperature and Reliability Aware Memory Design. DATE (2009)
Nicholas Callegari, Pouria Bastani, Li-C. Wang, Magdy S. Abadir
A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. ITC (2008)
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ISQED (2008)
Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir
Technology-Based MPSoCs Through Executable Specifications. IEEE Trans. Very Large Scale Integr. Syst. 16 (4) (2008)
Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir
Statistical diagnosis of unmodeled systematic timing effects. DAC (2008)
Pouria Bastani, Li-C. Wang, Magdy S. Abadir
Linking Statistical Learning to Diagnosis. IEEE Des. Test Comput. 25 (3) (2008)
Alper Sen, Vinit Ogale, Magdy S. Abadir
Predictive runtime verification of multi-processor SoCs in SystemC. DAC (2008)
Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray
A Survey of Hybrid Techniques for Functional Verification. IEEE Des. Test Comput. 24 (2) (2007)
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. VLSI Design (2007)
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ASP-DAC (2007)
Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
Statistical analysis and optimization of parametric delay test. ITC (2007)
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE (2007)
Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir
Analyzing the risk of timing modeling based on path delay tests. ITC (2007)
Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Des. Test Comput. 24 (2) (2007)
Li-C. Wang, Pouria Bastani, Magdy S. Abadir
Design-Silicon Timing Correlation A Data Mining Perspective. DAC (2007)
Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir
Extracting a Simplified View of Design Functionality Based on Vector Simulation. Haifa Verification Conference (2006)
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
Refined statistical static timing analysis through. DAC (2006)
Jayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir
A Trace-Driven Validation Methodology for Multi-Processor SOCS. SoCC (2006)
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. ITC (2006)
Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Magdy S. Abadir
Extracting a simplified view of design functionality via vector simulation. HLDVT (2006)
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir
Floorplan driven leakage power aware IP-based SoC design space exploration. CODES+ISSS (2006)
Magdy S. Abadir
Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. IOLTS (2006)
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV (2006)
Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris
Choosing flows and methodologies for SoC design. DAC (2005)
Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV (2005)
Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir
A methodology for validation of microprocessors using symbolic simulation. Int. J. Embed. Syst. 1 (1/2) (2005)
Brian Kahne, Magdy S. Abadir
Retiming Verification Using Sequential Equivalence Checking. MTV (2005)
Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI (2005)
Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea
Recent Advances in Verification, Equivalence Checking and SAT-Solvers. VLSI Design (2005)
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. VTS (2005)
Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
Post-Verification Debugging of Hierarchical Designs. MTV (2005)
Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir
Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. ITC (2005)
Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electron. Test. 21 (5) (2005)
Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
Post-verification debugging of hierarchical designs. ICCAD (2005)
Himyanshu Anand, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis
Establishing latch correspondence for embedded circuits of PowerPC microprocessors. HLDVT (2005)
Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design (2004)
Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
Debugging sequential circuits using Boolean satisfiability. ICCAD (2004)
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
Analytical models for leakage power estimation of memory array structures. CODES+ISSS (2004)
Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV (2004)
Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri
Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) (2004)
Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir
A Top-Down Methodology for Microprocessor Validation. IEEE Des. Test Comput. 21 (2) (2004)
Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC (2004)
Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith
Debugging Sequential Circuits Using Boolean Satisfiability. MTV (2004)
Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
On path-based learning and its applications in delay test and diagnosis. DAC (2004)
Magdy S. Abadir, Li-C. Wang
Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. IEEE Des. Test Comput. 21 (2) (2004)
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
IDAP: a tool for high-level power estimation of custom array structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (9) (2004)
M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu
Identification of Gates for Covering all Critical Paths. MTV (2004)
Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Des. Test Comput. 21 (6) (2004)
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE (2003)
Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin
Formal Verification Successes at Motorola. Formal Methods Syst. Des. 22 (2) (2003)
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir
IDAP: A Tool for High Level Power Estimation of Custom Array Structures. ICCAD (2003)
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC (2003)
Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir
Enhanced symbolic simulation for efficient verification of embedded array systems. ASP-DAC (2003)
Li-C. Wang, Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir, Manish Pandey
Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. Des. Autom. Embed. Syst. 8 (2-3) (2003)
Tim McDougall, Atanas N. Parashkevov, Simon Jolly, Juhong Zhu, Jing Zeng, Carol Pyron, Magdy S. Abadir
An automated method for test model generation from switch level circuits. ASP-DAC (2003)
Andreas G. Veneris, Alexander Smith, Magdy S. Abadir
Logic verification based on diagnosis techniques. ASP-DAC (2003)
Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV (2003)
Magdy S. Abadir, Juhong Zhu
Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. VTS (2003)
Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu
Automated Test Model Generation from Switch Level Custom Circuits. Asian Test Symposium (2003)
Li-C. Wang, Magdy S. Abadir
Validation and Verification of Complex Digital Systems: A Practical Perspective. LATW (2002)
Jing Zeng, Magdy S. Abadir, Jacob A. Abraham
False timing path identification using ATPG techniques and delay-based information. DAC (2002)
Jiang Brandon Liu, Andreas G. Veneris, Magdy S. Abadir
Efficient and Exact Diagnosis of Multiple Stuck-At Faults. LATW (2002)
Ad J. van de Goor, Magdy S. Abadir, Alan Carlin
Minimal Test for Coupling Faults in Word-Oriented Memories. DATE (2002)
Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir
Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE (2002)
Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC (2002)
Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS (2002)
Andreas G. Veneris, Magdy S. Abadir
Design rewiring using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (12) (2002)
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
Design Rewiring Using ATPG. ITC (2002)
Li-C. Wang, Magdy S. Abadir, Juhong Zhu
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. ITC (2002)
Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
ATPG for Design Errors-Is It Possible? VTS (2001)
Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir
Very Low Cost Testers: Opportunities and Challenges. IEEE Des. Test Comput. 18 (5) (2001)
Andreas G. Veneris, Magdy S. Abadir, Ivor Ting
Design rewiring based on diagnosis techniques. ASP-DAC (2001)
Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE (2001)
Magdy S. Abadir, Li-C. Wang
Verification and Validation of Complex Digital Systems: An Industrial Perspective. ISQED (2001)
Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham
Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Des. Test Comput. 18 (4) (2001)

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Publication Activity (10 Years)

Top Topics

Top Venues

Magdy S. Abadir