Anirban Sengupta

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 112

Top Venues

IEEE Consumer Electron. Mag.

IEEE Trans. Consumer Electron.

iSES

IEEE Access

Publications

Anirban Sengupta, Dushmanta Kumar Das
Delay-Dependent Wide-Area Damping Controller Considering Actuator Saturation and Communication Failure. IEEE Trans. Control. Netw. Syst. 11 (2) (2024)
Rahul Chaurasia, Anirban Sengupta
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS. Integr. 95 (2024)
Mahendra Rathor, Anirban Sengupta
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack. IEEE Embed. Syst. Lett. 16 (2) (2024)
Mahendra Rathor, Aditya Anshul, Anirban Sengupta
Securing Reusable IP Cores Using Voice Biometric Based Watermark. IEEE Trans. Dependable Secur. Comput. 21 (4) (2024)
Anirban Sengupta, Aditya Anshul
Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework. IEEE Access 12 (2024)
Anirban Sengupta, Rahul Chaurasia, Aditya Anshul
Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric Sample. AsianHOST (2023)
Anirban Sengupta, Aditya Anshul, Rahul Chaurasia
Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis. Microprocess. Microsystems 103 (2023)
Aditya Anshul, Anirban Sengupta
PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis. Expert Syst. Appl. 223 (2023)
Aditya Anshul, Anirban Sengupta
Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis. Microprocess. Microsystems 102 (2023)
Anirban Sengupta, Rahul Chaurasia
Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure. iSES (2023)
Anirban Sengupta, Mahendra Rathor, Rahul Chaurasia
Biometrics for Hardware Security and Trust: Discussion and Analysis. IT Prof. 25 (4) (2023)
Rahul Chaurasia, Anirban Sengupta
Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics. iSES (2023)
Rahul Chaurasia, Abhinav Reddy Asireddy, Anirban Sengupta
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template. DFT (2023)
Mahendra Rathor, Anirban Sengupta, Rahul Chaurasia, Aditya Anshul
Exploring Handwritten Signature Image Features for Hardware Security. IEEE Trans. Dependable Secur. Comput. 20 (5) (2023)
Aditya Anshul, Anirban Sengupta
Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO. iSES (2023)
Mahendra Rathor, Aditya Anshul, K. Bharath, Rahul Chaurasia, Anirban Sengupta
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. Comput. Electr. Eng. 105 (2023)
Anirban Sengupta, Rahul Chaurasia, Aditya Anshul
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key. IEEE Trans. Very Large Scale Integr. Syst. 31 (6) (2023)
Rahul Chaurasia, Anirban Sengupta
Retinal Biometric for Securing JPEG-Codec Hardware IP Core for CE Systems. IEEE Trans. Consumer Electron. 69 (3) (2023)
Anirban Sengupta, Rahul Chaurasia, K. Bharath
Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs. Comput. Electr. Eng. 111 (Part A) (2023)
Anirban Sengupta, Aditya Anshul
Key-Driven Multi-Layered Structural Obfuscation of IP cores using Reconfigurable Obfuscator based Network Challenge and Switch Control Logic. iSES (2023)
Anirban Sengupta, Aditya Anshul, Chirag Kothari, Sumer Thakur
Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration. ICM (2023)
Anirban Sengupta, Aditya Anshul, Sumer Thakur, Chirag Kothari
Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters. ICM (2023)
Asmita Manna, Anirban Sengupta, Chandan Mazumdar
A risk-based methodology for privacy requirements elicitation and control selection. Secur. Priv. 5 (1) (2022)
Preetam Mukherjee, Anirban Sengupta, Chandan Mazumdar
"Security Gap" as a metric for enterprise business processes. Secur. Priv. 5 (6) (2022)
Rahul Chaurasia, Aditya Anshul, Anirban Sengupta, Shikha Gupta
Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems. IEEE Consumer Electron. Mag. 11 (5) (2022)
Aditya Anshul, K. Bharath, Anirban Sengupta
Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems. iSES (2022)
Aditya Anshul, Anirban Sengupta
IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints. iSES (2022)
Anirban Sengupta, Rahul Chaurasia
Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric. IEEE Trans. Consumer Electron. 68 (3) (2022)
Rahul Chaurasia, Anirban Sengupta
Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core. iSES (2022)
Anirban Sengupta, Rahul Chaurasia
Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression. IEEE Access 10 (2022)
Rahul Chaurasia, Anirban Sengupta
Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing. iSES (2022)
Anirban Sengupta, Rahul Chaurasia, Tarun Reddy
Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems. IEEE Trans. Consumer Electron. 67 (3) (2021)
Arindam Das, Manoj Kumar Gangwar, Devleena Ghosh, Chittaranjan Mandal, Anirban Sengupta, M. Mubashshir Waris
Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan. IEEE Trans. Intell. Transp. Syst. 22 (10) (2021)
Anirban Sengupta, Arabinda Mishra, Feng Wang, Muwei Li, Pai-Feng Yang, Li Min Chen, John C. Gore
Functional networks in non-human primate spinal cord and the effects of injury. NeuroImage 240 (2021)
Mahendra Rathor, Anirban Sengupta
Signature Biometric based Authentication of IP Cores for Secure Electronic Systems. iSES (2021)
Wei Hu, Chip-Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner, Hai Li
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (6) (2021)
Anirban Sengupta, Mahendra Rathor
Facial Biometric for Securing Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29 (1) (2021)
Anirban Sengupta
A Stakeholder-Centric Approach for Defining Metrics for Information Security Management Systems. CRiSIS (2021)
Rahul Chaurasia, Anirban Sengupta
Securing Reusable Hardware IP cores using Palmprint Biometric. iSES (2021)
Anirban Sengupta, Mahendra Rathor
Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems. IEEE Trans. Consumer Electron. 66 (2) (2020)
Anirban Sengupta, Mahendra Rathor
Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems. IEEE Access 8 (2020)
Anirban Sengupta, Mahendra Rathor
Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors. IEEE Trans. Consumer Electron. 66 (4) (2020)
Puloma Roy, Anirban Sengupta, Chandan Mazumdar
A Structured Control Selection Methodology for Insider Threat Mitigation. CENTERIS/ProjMAN/HCist (2020)
Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography. ICCE-Berlin (2020)
Mahendra Rathor, Anirban Sengupta
IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems. IEEE Trans. Consumer Electron. 66 (3) (2020)
Anirban Sengupta, Mahendra Rathor
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Anirban Sengupta, Deepak Kachave, Dipanjan Roy
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Anirban Sengupta, E. Ranjith Kumar, N. Prajwal Chandra
Embedding Digital Signature Using Encrypted-Hashing for Protection of DSP Cores in CE. IEEE Trans. Consumer Electron. 65 (3) (2019)
Mahendra Rathor, Anirban Sengupta
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic. ICCE-Berlin (2019)
Anirban Sengupta, Mahendra Rathor
Improved Delay Estimation Model for Loop based DSP cores. ICCE (2019)
Anirban Sengupta, Mahendra Rathor
Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware. IEEE Access 7 (2019)
Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 8 (1) (2019)
Anirban Sengupta, Mahendra Rathor
IP Core Steganography for Protecting DSP Kernels Used in CE Systems. IEEE Trans. Consumer Electron. 65 (4) (2019)
Asmita Manna, Anirban Sengupta, Chandan Mazumdar
A Quantitative Methodology for Business Process-Based Data Privacy Risk Computation. ACSS (2) (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Mahendra Rathor, Anirban Sengupta
Robust Logic locking for Securing Reusable DSP Cores. IEEE Access 7 (2019)
Anirban Sengupta, Gargi Gupta, Harshit Jalan
Hardware Steganography for IP Core Protection of Fault Secured DSP Cores. ICCE-Berlin (2019)
Anirban Sengupta, N. Prajwal Chandra, E. Ranjith Kumar
Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning. ICCE-Berlin (2019)
Anirban Sengupta, Utkarsh Kumar Singh, Piyush Kalkute Premchand
Crypto based Multi-Variable Fingerprinting for Protecting DSP cores. ICCE-Berlin (2019)
Dipanjan Roy, Anirban Sengupta
Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters]. IEEE Consumer Electron. Mag. 8 (2) (2019)
Anirban Sengupta, Mahendra Rathor
Protecting DSP Kernels Using Robust Hologram-Based Obfuscation. IEEE Trans. Consumer Electron. 65 (1) (2019)
Anirban Sengupta
Design Pruning of DSP Kernel for Multi Objective IP Core Architecture. ICCE (2019)
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design. ICCE (2019)
Anirban Sengupta, Dipanjan Roy
Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters]. IEEE Consumer Electron. Mag. 7 (1) (2018)
Anirban Sengupta, Dipanjan Roy
Reusable intellectual property core protection for both buyer and seller. ICCE (2018)
Anirban Sengupta, Deepak Kachave
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis. Future Gener. Comput. Syst. 80 (2018)
Deepak Kachave, Anirban Sengupta
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]. IEEE Consumer Electron. Mag. 7 (2) (2018)
Anirban Sengupta, Dipanjan Roy
Multi-phase watermark for IP core protection. ICCE (2018)
Anirban Sengupta, Niranjan Kumar Ray
Audio and Video Technologies: Recent Advances in Consumer Electronics. IEEE Consumer Electron. Mag. 7 (5) (2018)
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (4) (2018)
Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar
Optimizing DSP Cores Using Design Transformation [Hardware Matters]. IEEE Consumer Electron. Mag. 7 (4) (2018)
Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation. ISVLSI (2018)
Anirban Sengupta, Deepak Kachave
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores. iSES (2018)
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran
Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware. IEEE Trans. Consumer Electron. 64 (3) (2018)
Anirban Sengupta, Saraju P. Mohanty
Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption. ISVLSI (2018)
Dipanjan Roy, Anirban Sengupta
Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter]. IEEE Consumer Electron. Mag. 7 (3) (2018)
Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. IET Comput. Digit. Tech. 12 (6) (2018)
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran
A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC. IEEE Access 6 (2018)
Anirban Sengupta, Deepak Kachave
Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath. IEEE Trans. Aerosp. Electron. Syst. 54 (3) (2018)
Anirban Sengupta, Saraju P. Mohanty, Fernando Pescador, Peter Corcoran
Multi-Phase Obfuscation of Fault Secured DSP Designs With Enhanced Security Feature. IEEE Trans. Consumer Electron. 64 (3) (2018)
Srijita Basu, Anirban Sengupta, Chandan Mazumdar
A Quantitative Methodology for Cloud Security Risk Assessment. CLOSER (2017)
Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (4) (2017)
Anirban Sengupta, Sandip Kundu
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
A Firefly Algorithm Driven Approach for High Level Synthesis. iNIS (2017)
Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty
Low-cost security aware HLS methodology. IET Comput. Digit. Tech. 11 (2) (2017)
Anirban Sengupta, Dipanjan Roy, Saumya Bhadauria
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper). Integr. 58 (2017)
Anirban Sengupta, Deepak Kachave
-unit transient for loop based control data flow graphs during physically aware high level synthesis. Microelectron. Reliab. 74 (2017)
Anirban Sengupta, Dipanjan Roy
Mathematical Validation of HWT Based Lossless Image Compression. iNIS (2017)
Anirban Sengupta
Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters]. IEEE Consumer Electron. Mag. 6 (3) (2017)
Anirban Sengupta, Dipanjan Roy
Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters]. IEEE Consumer Electron. Mag. 6 (2) (2017)
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 6 (4) (2017)
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran
DSP design protection in CE through algorithmic transformation based structural obfuscation. IEEE Trans. Consumer Electron. 63 (4) (2017)
Anirban Sengupta
Hardware Security of CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 6 (1) (2017)
Vipul Kumar Mishra, Anirban Sengupta
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis. iNIS (2017)
Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha
Reliability and Threat Analysis of NBTI Stress on DSP Cores. iNIS (2017)
Dipanjan Roy, Anirban Sengupta
Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis. Future Gener. Comput. Syst. 71 (2017)
Anirban Sengupta, Dipanjan Roy
Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools. Adv. Eng. Softw. 110 (2017)
Saraju P. Mohanty, Anirban Sengupta, Parthasarathy Guturu, Elias Kougianos
Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection: From paper marks to hardware protection. IEEE Consumer Electron. Mag. 6 (3) (2017)
Srijita Basu, Anirban Sengupta, Chandan Mazumdar
An Automated Methodology for Secured User Allocation in Cloud. SSCC (2016)
Deepak Kachave, Anirban Sengupta
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors. Microelectron. Reliab. 60 (2016)

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Publication Activity (10 Years)

Top Topics

Top Venues

Anirban Sengupta