José Pineda de Gyvez

ORCID

Publication Activity (10 Years)

Years Active: 1989-2023
Publications (10 Years): 35

Top Venues

DATE

IEEE Trans. Very Large Scale Integr. Syst.

ISQED

IEEE Trans. Computers

Publications

Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods. IEEE Trans. Circuits Syst. II Express Briefs 70 (7) (2023)
Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT. ISQED (2021)
Kamlesh Singh, José Pineda de Gyvez
Twenty Years of Near/Sub-Threshold Design Trends and Enablement. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Barry de Bruin, Kamlesh Singh, Ying Wang, Jos Huisken, José Pineda de Gyvez, Henk Corporaal
Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection. IEEE Trans. Biomed. Circuits Syst. 15 (5) (2021)
Kamlesh Singh, Barry de Bruin, Hailong Jiao, Jos Huisken, Henk Corporaal, José Pineda de Gyvez
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Shima Sedighiani, Kamlesh Singh, Jos Huisken, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT. MECO (2020)
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez
Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Paul Detterer, Cumhur Erdin, Jos Huisken, Hailong Jiao, Majid Nabi, Twan Basten, José Pineda de Gyvez
Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. DATE (2020)
Emad A. Ibrahim, Marc Geilen, Jos Huisken, Min Li, José Pineda de Gyvez
Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN. DATE (2020)
Emad A. Ibrahim, Marc Geilen, Min Li, José Pineda de Gyvez
Multi-Angle Fusion for Low-Cost Near-Field Ultrasonic in-Air Gesture Recognition. IEEE Access 8 (2020)
Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez
-active dynamic power. SLIP (2020)
Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
Hadi Ahmadi Balef, Kees Goossens, José Pineda de Gyvez
Chip Health Tracking Using Dynamic In-Situ Delay Monitoring. DATE (2019)
P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs. Integr. 67 (2019)
Emad A. Ibrahim, Min Li, José Pineda de Gyvez
PRESS/HOLD/RELEASE Ultrasonic Gestures and Low Complexity Recognition Based on TCN. SiPS (2019)
Paul Detterer, Cumhur Erdin, Majid Nabi, José Pineda de Gyvez, Twan Basten, Hailong Jiao
Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. DATE (2019)
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66 (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Emad A. Ibrahim, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network. DSD (2019)
Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, José Pineda de Gyvez
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. SoCC (2019)
P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs. PATMOS (2018)
Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken, José Pineda de Gyvez
Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. ISCAS (2018)
Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
Low power latch based design with smart retiming. ISQED (2018)
Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths. ACM Great Lakes Symposium on VLSI (2018)
Xun Jiao, Abbas Rahimi, Yu Jiang, Jianguo Wang, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units. IEEE Trans. Computers 67 (6) (2018)
Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens
An analytical model for interdependent setup/hold-time characterization of flip-flops. ISQED (2017)
Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez
Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC (2017)
Pascal Alexander Hager, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
A scan-chain based state retention methodology for IoT processors operating on intermittent energy. DATE (2017)
Andres Gomez, Andrea Bartolini, Davide Rossi, Baris Can Kara, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors. Microprocess. Microsystems 53 (2017)
Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez
Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Martin Van Leussen, Jos Huisken, Lei Wang, Hailong Jiao, José Pineda de Gyvez
Reconfigurable Support Vector Machine Classifier with Approximate Computing. ISVLSI (2017)
Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, Kofi A. A. Makinwa, José Pineda de Gyvez
A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling. IEEE J. Solid State Circuits 52 (4) (2017)
Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez
Lower power by voltage stacking: a fine-grained system design approach. DAC (2016)
José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt
Circuit valorization in the IC design ecosystem. ICCAD (2016)
Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi A. A. Makinwa
A microcontroller with 96% power-conversion efficiency using stacked voltage domains. VLSI Circuits (2016)
Xun Jiao, Abbas Rahimi, Balakrishnan Narayanaswamy, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
Supervised learning based model for predicting variability-induced timing errors. NEWCAS (2015)
Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim
Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. VLSI-SoC (2015)
Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez
An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. 20 (4) (2015)
Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. Microprocess. Microsystems 39 (8) (2015)
Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. DATE (2015)
Yu Pu, Juan Diego Echeverri, Maurice Meijer, José Pineda de Gyvez
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling. DATE (2014)
Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez
Digital Systems Power Management for High Performance Mixed Signal Platforms. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez
Standard cell library tuning for variability tolerant designs. DATE (2014)
Bo Liu, Maryam Ashouei, Tobias Gemmeke, José Pineda de Gyvez
Sub-threshold custom standard cell library validation. ISQED (2014)
Hamid Reza Pourshaghaghi, José Pineda de Gyvez
Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking. IEEE Trans. Computers 62 (12) (2013)
Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez
A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers. NORCHIP (2013)
Ajay Kapoor, José Pineda de Gyvez
Architectural Analysis for Wirelessly Powered Computing Platforms. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Maurice Meijer, José Pineda de Gyvez
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Sebastian M. Londono, José Pineda de Gyvez
A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. SoCC (2012)
Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS. IEEE Trans. Instrum. Meas. 61 (8) (2012)
Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez
Sliding-Mode Control to Compensate PVT Variations in dual core systems. DATE (2012)
Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. J. Low Power Electron. 8 (2) (2012)
Bo Liu, Maryam Ashouei, Jos Huisken, José Pineda de Gyvez
Standard cell sizing for subthreshold operation. DAC (2012)
Amir Zjajo, José Pineda de Gyvez
A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. ISLPED (2011)
Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, Nick van der Meijs
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2011)
Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez
Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. DSD (2011)
Hamid Reza Pourshaghaghi, José Pineda de Gyvez
Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. ICECS (2010)
Maurice Meijer, José Pineda de Gyvez, Ajay Kapoor
Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation. J. Low Power Electron. 6 (4) (2010)
Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt
A forward body bias generator for digital CMOS circuits with supply voltage scaling. ISCAS (2010)
Maurice Meijer, José Pineda de Gyvez
Body bias driven design synthesis for optimum performance per area. ISQED (2010)
Sebastian M. Londono, José Pineda de Gyvez
An energy-aware multiplier based on a Configurable-Reuse of points design methodology. ICECS (2009)
Amir Zjajo, José Pineda de Gyvez
Analog Automatic Test Pattern Generation for Quasi-Static Structural Test. IEEE Trans. Very Large Scale Integr. Syst. 17 (10) (2009)
Hamid Reza Pourshaghaghi, José Pineda de Gyvez
Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller. ICECS (2009)
Amir Zjajo, José Pineda de Gyvez
Calibration and Debugging of Multi-step Analog to Digital Converters. DELTA (2008)
Amir Zjajo, José Pineda de Gyvez
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. DATE (2008)
Amir Zjajo, Shaji Krishnan, José Pineda de Gyvez
Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. DDECS (2008)
Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. DATE (2007)
Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
Efficient testing and diagnosis of faulty power switches in SOCs. IET Comput. Digit. Tech. 1 (3) (2007)
Josep Rius, Maurice Meijer, José Pineda de Gyvez
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. J. Low Power Electron. 2 (1) (2006)
Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
Testing and Diagnosis of Power Switches in SOCs. ETS (2006)
Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. J. Electron. Test. 22 (4-6) (2006)
Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. IEEE J. Solid State Circuits 41 (10) (2006)
Estella Silva, José Pineda de Gyvez, Guido Gronthoud
Functional vs. multi-VDD testing of RF circuits. ITC (2005)
Maurice Meijer, José Pineda de Gyvez, Ralph Otten
On-chip digital power supply control for system-on-chip applications. ISLPED (2005)
Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
Glitch-free discretely programmable clock generation on chip. ISCAS (2) (2005)
Wei Zhuo, Xiaoyong Li, Sudip Shekhar, Sherif H. K. Embabi, José Pineda de Gyvez, David J. Allstot, Edgar Sánchez-Sinencio
A capacitor cross-coupled common-gate low-noise amplifier. IEEE Trans. Circuits Syst. II Express Briefs (12) (2005)
José Pineda de Gyvez, Guido Gronthoud, Rashid Amine
Multi-VDD Testing for Analog Circuits. J. Electron. Test. 21 (3) (2005)
Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
Limits to performance spread tuning using adaptive voltage and body biasing. ISCAS (1) (2005)
Amir Zjajo, José Pineda de Gyvez
Evaluation of signature-based testing of RF/analog circuits. ETS (2005)
Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane
Programmable techniques for cell stability test and debug in embedded SRAMs. CICC (2005)
Amir Zjajo, Henk Jan Bergveld, Rodger Schuttert, José Pineda de Gyvez
Power-scan chain: design for analog testability. ITC (2005)
Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev
Word line pulsing technique for stability fault detection in SRAM cells. ITC (2005)
Josep Rius, José Pineda de Gyvez, Maurice Meijer
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. PATMOS (2005)
Josep Rius Vázquez, José Pineda de Gyvez
Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. VTS (2004)
Josep Rius Vázquez, José Pineda de Gyvez
testing. IEEE J. Solid State Circuits 39 (3) (2004)
Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
Low energy FPGA interconnect design. ACM Great Lakes Symposium on VLSI (2004)
José Pineda de Gyvez, Hans Tuinhout
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits. IEEE J. Solid State Circuits 39 (1) (2004)
Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. ITC (2004)
Josep Rius Vázquez, José Pineda de Gyvez
Power Supply Noise Monitor for Signal Integrity Faults. DATE (2004)
José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller
Power Supply Ramping for Quasi-static Testing of PLLs. ITC (2004)
Rohini Krishnan, José Pineda de Gyvez
Low Energy Switch Block For FPGAs. VLSI Design (2004)
Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
Low energy FPGA interconnect design. FPGA (2004)
Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
Technology exploration for adaptive power and frequency scaling in 90nm CMOS. ISLPED (2004)
José Pineda de Gyvez, Guido Gronthoud, Rashid Amine
VDD Ramp Testing for RF Circuits. ITC (2003)
Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick
Encoded-Low Swing Technique for Ultra Low Power Interconnect. FPL (2003)
Daniel Arumí-Delgado, Rosa Rodríguez-Montañés, José Pineda de Gyvez, Guido Gronthoud
and weak-open defects. ETW (2003)
Phillip Christie, José Pineda de Gyvez
Prelayout interconnect yield prediction. IEEE Trans. Very Large Scale Integr. Syst. 11 (1) (2003)
Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio
An Analog Integrated Circuit Design Laboratory. MSE (2003)
José Pineda de Gyvez, Rosa Rodríguez-Montañés
Threshold Voltage Mismatch (DeltaVT) Fault Modeling. VTS (2003)
Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez
Resistance Characterization for Weak Open Defects. IEEE Des. Test Comput. 19 (5) (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

José Pineda de Gyvez