Hailong Jiao

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 56

Top Topics

Error Compensation

Statistical Modeling

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Changchun Zhou, Yuzhe Fu, Yanzhe Ma, Eryi Han, Yifan He, Hailong Jiao
Adjustable Multi-Stream Block-Wise Farthest Point Sampling Acceleration in Point Cloud Analysis. IEEE Trans. Circuits Syst. II Express Briefs 71 (7) (2024)
Zhuoya Yan, Yingna Huang, Hailong Jiao
A Low-Power Single-Phase Split-Controlled Flip-Flop With No Redundant Switching. ISCAS (2024)
Cong Huang, Hailong Jiao
MLS: An Ultra-Wide-Range Energy-Efficient Level Shifter With CCLS/CMLS Hybrid Structure. IEEE J. Solid State Circuits 58 (10) (2023)
Ming Liu, Changchun Zhou, Siyuan Qiu, Yifan He, Hailong Jiao
CNN Accelerator at the Edge With Adaptive Zero Skipping and Sparsity-Driven Data Flow. IEEE Trans. Circuits Syst. Video Technol. 33 (12) (2023)
Changchun Zhou, Min Liu, Siyuan Qiu, Xugang Cao, Yuzhe Fu, Yifan He, Hailong Jiao
Sagitta: An Energy-Efficient Sparse 3D-CNN Accelerator for Real-Time 3-D Understanding. IEEE Internet Things J. 10 (23) (2023)
Siyuan Qiu, Wenjin Wang, Hailong Jiao
LightSeizureNet: A Lightweight Deep Learning Model for Real-Time Epileptic Seizure Detection. IEEE J. Biomed. Health Informatics 27 (4) (2023)
Xiaojin Zhao, Hailong Jiao, Wei Mao
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (11) (2023)
Changchun Zhou, Yuzhe Fu, Min Liu, Siyuan Qiu, Ge Li, Yifan He, Hailong Jiao
An Energy-Efficient 3D Point Cloud Neural Network Accelerator With Efficient Filter Pruning, MLP Fusion, and Dual-Stream Sampling. ICCAD (2023)
Ming Liu, Yifan He, Hailong Jiao
An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator. APCCAS (2022)
Adam Cron, Hailong Jiao, Erik Jan Marinissen
Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages. IEEE Des. Test 39 (5) (2022)
Chenyu Xie, Chunmei Yang, Hailong Jiao
A Karnaugh Map Approximate Adder With Intrinsic Error Compensation. APCCAS (2022)
Xudong Wang, Geng Li, Jiacong Sun, Huanjie Fan, Yong Chen, Hailong Jiao
Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks. APCCAS (2022)
Jiacong Sun, Hao Guo, Geng Li, Hailong Jiao
An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit. IEEE J. Solid State Circuits 57 (11) (2022)
Paul Detterer, Majid Nabi, Hailong Jiao, Twan Basten
Receiver Design With an Adjustable Energy-Signal-Quality Tradeoff for IoT Networks. IEEE Internet Things J. 9 (22) (2022)
Xugang Cao, Hailong Jiao, Erik Jan Marinissen
A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Yuting Chen, Yuxuan Nie, Hailong Jiao
An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits. IEEE Trans. Very Large Scale Integr. Syst. 30 (5) (2022)
Hing-Mo Lam, Silin Lu, Hezi Qiu, Min Zhang, Hailong Jiao, Shengdong Zhang
A High-Efficiency Segmented Reconfigurable Cyclic Shifter for 5G QC-LDPC Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Min Liu, Yifan He, Hailong Jiao
Efficient Zero-Activation-Skipping for On-Chip Low-Energy CNN Acceleration. AICAS (2021)
Chen Xu, Xiaolei Su, Zhengkun Shen, Dong Wang, Yi Tan, Zexue Liu, Hailong Jiao, Junhua Liu, Huailin Liao
A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications. ISCAS (2021)
Hing-Mo Lam, Silin Lu, Hezi Qiu, Hailong Jiao, Min Zhang, Shengdong Zhang
Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder. ISCAS (2021)
Hing-Mo Lam, Fan Guo, Hezi Qiu, Min Zhang, Hailong Jiao, Shengdong Zhang
Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers. IEEE Trans. Circuits Syst. Video Technol. 31 (5) (2021)
Silin Lu, Lei Lu, Shengdong Zhang, Hailong Jiao
A Pull-Up Adaptive Sense Amplifier Based on Dual-Gate IGZO TFTs. ISCAS (2021)
Yunbo Huang, Yong Chen, Hailong Jiao, Pui-In Mak, Rui Paulo Martins
A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Kamlesh Singh, Barry de Bruin, Hailong Jiao, Jos Huisken, Henk Corporaal, José Pineda de Gyvez
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Kris van Noord, Wenjin Wang, Hailong Jiao
Insights of 3D Input CNN in EEG-based Emotion Recognition. EMBC (2021)
Changchun Zhou, Min Liu, Siyuan Qiu, Yifan He, Hailong Jiao
An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance. DAC (2021)
Paul Detterer, Majid Nabi, Hailong Jiao, Twan Basten
Receiver-Sensitivity Control for Energy-Efficient IoT Networks. IEEE Commun. Lett. 25 (4) (2021)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Hezi Qiu, Jian Liang, Wenlong Bai, Hing-Mo Lam, Junjun An, Congwei Liao, Min Zhang, Hailong Jiao, Shengdong Zhang
A Compensation System using Analog Voltage Adder with Continuous Output for AMOLED Display Drivers. ISCAS (2020)
Hailong Jiao, Zhanliang Zhang
A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode. ISCAS (2020)
Paul Detterer, Cumhur Erdin, Jos Huisken, Hailong Jiao, Majid Nabi, Twan Basten, José Pineda de Gyvez
Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. DATE (2020)
Jian Liang, Shuiping Yi, Wenlong Bai, Lidan Wang, Chenchang Zhan, Congwei Liao, Hing-Mo Lam, Min Zhang, Shengdong Zhang, Hailong Jiao
A -80 dB PSRR 4.99 ppm/°C TC bandgap reference with nonlinear compensation. Microelectron. J. 95 (2020)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. ICEIC (2019)
Paul Detterer, Cumhur Erdin, Majid Nabi, José Pineda de Gyvez, Twan Basten, Hailong Jiao
Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. DATE (2019)
Yuting Chen, Hailong Jiao
Standard Cell Optimization for Ultra-Low-Voltage Digital Circuits. ICICDT (2019)
Chunmei Yang, Hailong Jiao
Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations. ICICDT (2019)
Jiacong Sun, Hailong Jiao
A 12T Low-Power Standard-Cell Based SRAM Circuit for Ultra-Low-Voltage Operations. ICICDT (2019)
Xinxin Huo, Wenlong Bai, Hing-Mo Lam, Congwei Liao, Min Zhang, Shengdong Zhang, Hailong Jiao
A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays. ISCAS (2019)
Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, José Pineda de Gyvez
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. SoCC (2019)
Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken, José Pineda de Gyvez
Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. ISCAS (2018)
Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
Low power latch based design with smart retiming. ISQED (2018)
Hailong Jiao, Rui Wang, Yifan He
Crosstalk-noise-aware bus coding with low-power ground-gated repeaters. Int. J. Circuit Theory Appl. 46 (2) (2018)
Luc Waeijen, Hailong Jiao, Henk Corporaal, Yifan He
Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude. DSD (2018)
Paul Detterer, Cumhur Erdin, Majid Nabi, Twan Basten, Hailong Jiao
Understanding the Impact of Circuit-Level Inaccuracy on Sensor Network Performance. PE-WASUN (2018)
Leonidas Katselas, Alkis A. Hatzopoulos, Hailong Jiao, Christos Papameletis, Erik Jan Marinissen
On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. ITC (2018)
Fanglei Hu, Min Zhang, Hailong Jiao
Achieving Low Power Classification with Classifier Ensemble. ISVLSI (2018)
Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. ETS (2018)
Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens
An analytical model for interdependent setup/hold-time characterization of flip-flops. ISQED (2017)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. ASICON (2017)
Leonidas Katselas, Hailong Jiao, Angelos Athanasiadis, Christos Papameletis, Alkis A. Hatzopoulos, Erik Jan Marinissen
Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. PATMOS (2017)
Martin Van Leussen, Jos Huisken, Lei Wang, Hailong Jiao, José Pineda de Gyvez
Reconfigurable Support Vector Machine Classifier with Approximate Computing. ISVLSI (2017)
Peng Ling, Chong Shen, Kun Zhang, Hailong Jiao, Liqiang Zheng, Xi Deng
An improved NLOS error elimination algorithm for indoor ultra-wideband localization. IEEE SENSORS (2017)
Hailong Jiao, Yongmin Qiu, Volkan Kursun
Low power and robust memory circuits with asymmetrical ground gating. Microelectron. J. 48 (2016)
Erik Jan Marinissen, Teresa L. McLaurin, Hailong Jiao
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. ETS (2016)
Hailong Jiao, Yongmin Qiu, Volkan Kursun
Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode. Integr. 53 (2016)
Hailong Jiao, Yongmin Qiu, Volkan Kursun
Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode. IOLTS (2016)
Yanan Sun, Hailong Jiao, Volkan Kursun
A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Said Hamdioui, Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Koen Bertels, Henk Corporaal, Hailong Jiao, Francky Catthoor, Dirk J. Wouters, Eike Linn, Jan van Lunteren
Memristor based computation-in-memory architecture for data-intensive applications. DATE (2015)
Hailong Jiao, Volkan Kursun
Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits. Microelectron. J. 45 (8) (2014)
Yanan Sun, Hailong Jiao, Volkan Kursun
Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins. ICM (2014)
Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun
Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability. ISCAS (2013)
Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun
A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. ISQED (2013)
Hailong Jiao, Volkan Kursun
Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Hailong Jiao, Volkan Kursun
Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits. VLSI-SoC (2013)
Hailong Jiao, Volkan Kursun
Ground gated 8T SRAM cells with enhanced read and hold data stability. ISVLSI (2013)
Bo Xie, Hailong Jiao, Junbo Wang, Deyong Chen, Jian Chen
An electrostatically-driven and capacitively-sensed differential lateral resonant pressure microsensor. NEMS (2013)
Hailong Jiao, Volkan Kursun
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Hailong Jiao, Volkan Kursun
Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits. ISOCC (2012)
Hailong Jiao, Volkan Kursun
Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations. ISCAS (2012)
Hailong Jiao, Volkan Kursun
Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits. SoCC (2011)
Hailong Jiao, Volkan Kursun
Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias. J. Circuits Syst. Comput. 20 (1) (2011)
Hailong Jiao, Volkan Kursun
Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Hailong Jiao, Volkan Kursun
Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2010)
Hailong Jiao, Volkan Kursun
Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits. VLSI-SoC (Selected Papers) (2010)
Hailong Jiao, Volkan Kursun
Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops. ISCAS (2010)
Hailong Jiao, Volkan Kursun
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits. VLSI-SoC (2010)
Hailong Jiao, Volkan Kursun
Low-Leakage and Compact Registers with Easy-Sleep Mode. J. Low Power Electron. 6 (2) (2010)
Hailong Jiao, Lan Chen
Cellwise OPC Based on Reduced Standard Cell Library. ISQED (2008)