Zhigang Mao

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 72

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ASICON

DATE

Publications

Kunyue Li, Zhengji Zhao, Qixuan Cai, Qin Wang, Naifeng Jing, Zhigang Mao, Jianfei Jiang
A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. Expert Syst. Appl. 249 (2024)
Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. ASPDAC (2024)
Zihan Zhang, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (1) (2024)
Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. ASPDAC (2024)
Yanan Sun, Zhi Li, Weiyi Liu, Weifeng He, Qin Wang, Zhigang Mao
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. FPL (2023)
Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng
An Efficient near-Bank Processing Architecture for Personalized Recommendation System. ASP-DAC (2023)
Xiaoyan Li, Zizheng Dong, Shuaipeng Li, Sai Gao, Jianfei Jiang, Guanghui He, Zhigang Mao
MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5. ASICON (2023)
Yuxuan Qin, Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Jiayu Zhang, Shaojun Cheng, Feng Dong, Ke Chen, Yong Qiao, Zhigang Mao, Jianfei Jiang
A Hierarchical Communication Algorithm for Distributed Deep Learning Training. MWSCAS (2023)
Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang
RTMDet-R2: An Improved Real-Time Rotated Object Detector. PRCV (12) (2023)
Chen Yin, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (3) (2023)
Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Shuai Yuan, Yanan Sun, Weifeng He, Qianrong Gu, Shi Xu, Zhigang Mao, Shikui Tu
MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification. IEEE Trans. Geosci. Remote. Sens. 60 (2022)
Taozhong Li, Naifeng Jing, Zhigang Mao, Yiran Chen
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Zihan Zhang, Jianfei Jiang, Yongxin Zhu, Qin Wang, Zhigang Mao, Naifeng Jing
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. 19 (2022)
Taozhong Li, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao, Yiran Chen
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. ACM Trans. Design Autom. Electr. Syst. 27 (6) (2022)
Linzhe Li, Liyi Xiao, He Liu, Zhigang Mao
Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits. IEEE Access 10 (2022)
Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. DAC (2021)
Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Chengbin Duan, Wenli Chen, Shun Yao, Zhigang Mao, Zongming Wang, Bin Hu, Haosen Jiao, Dimin Zhu, Yonghong Zhu, Haijun Wang
Automatic Detection for Acromegaly Using Hand Photographs: A Deep-Learning Approach. IEEE Access 9 (2021)
Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Pavan Kumar Chundi, Zhigang Mao, Mingoo Seok
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits 56 (7) (2021)
Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. DATE (2021)
Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing
A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. BigDataSecurity (2021)
Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. DATE (2021)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Juhua Luo, Ruiliang Pu, Hongtao Duan, Ronghua Ma, Zhigang Mao, Yuan Zeng, Linsheng Huang, Qitao Xiao
Evaluating the influences of harvesting activity and eutrophication on loss of aquatic vegetations in Taihu Lake, China. Int. J. Appl. Earth Obs. Geoinformation 87 (2020)
Juhua Luo, Ruiliang Pu, Ronghua Ma, Xiaolong Wang, Xijun Lai, Zhigang Mao, Li Zhang, Zhaoliang Peng, Zhe Sun
Mapping Long-Term Spatiotemporal Dynamics of Pen Aquaculture in a Shallow Lake: Less Aquaculture Coming along Better Water Quality. Remote. Sens. 12 (11) (2020)
Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. ACM Great Lakes Symposium on VLSI (2020)
Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Zhigang Mao, Mingoo Seok
25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. ISSCC (2020)
Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 31 (9) (2020)
Yijia Zhang, Weiguang Sheng, Jian-Fei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. 12 (7) (2020)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. ICEIC (2019)
Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs (5) (2019)
Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna
mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. ISPASS (2019)
Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. ASICON (2019)
Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. ASICON (2019)
Yongjie Lu, Yanan Sun, Weifeng He, Zhigang Mao
A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. NANOARCH (2019)
Taozhong Li, Qin Wang, Yongxin Zhu, Jian-Fei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Jing Guo, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. IEEE Trans. Very Large Scale Integr. Syst. 26 (5) (2018)
Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. ReConFig (2018)
Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao
Optimizing the data placement and transformation for multi-bank CGRA computing system. DATE (2018)
Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
Pipelines Based on Wide-Pulsed-Latch Design Techniques. IEEE J. Solid State Circuits 52 (9) (2017)
Jing Guo, Lei Zhu, Wenyi Liu, Hai Huang, Shanshan Liu, Tianqi Wang, Liyi Xiao, Zhigang Mao
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Qin Wang, Zhenyang Chen, Jian-Fei Jiang, Zheng Guo, Zhigang Mao
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. Integr. 59 (2017)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. ASICON (2017)
Shanshan Liu, Liyi Xiao, Xuebing Cao, Zhigang Mao
Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability. ASP-DAC (2017)
Wei Jin, Guanghui He, Weifeng He, Zhigang Mao
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. Integr. 59 (2017)
Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao
Low redundancy matrix-based codes for adjacent error correction with parity sharing. ISQED (2017)
Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li
A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE (2017)
Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. Microelectron. J. 62 (2017)
Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT (2016)
Zhiting Yan, Guanghui He, Weifeng He, Shuaijie Wang, Zhigang Mao
High performance parallel turbo decoder with configurable interleaving network for LTE application. Integr. 52 (2016)
Liang Hong, Wei-Feng He, Guanghui He, Zhigang Mao
Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding. IEICE Electron. Express 13 (6) (2016)
Shanshan Liu, Liyi Xiao, Zhigang Mao
Extend orthogonal Latin square codes for 32-bit data protection in memory applications. Microelectron. Reliab. 63 (2016)
Jian-Fei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. 25 (10) (2016)
Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. A-SSCC (2016)
Weiguang Sheng, Jian-Fei Jiang, Zhigang Mao
Parallel SER analysis for combinational and sequential standard cell circuits. Microelectron. J. 50 (2016)
Zhiting Yan, Guanghui He, Weifeng He, Zhigang Mao
Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2015)
Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao
Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig (2015)
Jiayi Hu, Qin Wang, Jian-Fei Jiang, Jing Xie, Zhigang Mao
A crosstalk avoidance scheme based on re-layout of signal TSV. ASICON (2015)
Naifeng Jing, Jiacheng Zhou, Jian-Fei Jiang, Xin Chen, Weifeng He, Zhigang Mao
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD (2015)
Shanshan Liu, Liyi Xiao, Jing Guo, Zhigang Mao
Fault Secure Encoder and Decoder Designs for Matrix Codes. CAD/Graphics (2015)
Jing Guo, Liyi Xiao, Tianqi Wang, Shanshan Liu, Xu Wang, Zhigang Mao
Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology. IEEE Trans. Reliab. 64 (2) (2015)
Jian-Fei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao
Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express 12 (8) (2015)
Jian-Fei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao
A contactless testing methodology for pre-bond interposer. MWSCAS (2015)
Sai Hu, Qin Wang, Zheng Guo, Jing Xie, Zhigang Mao
Fault detection and redundancy design for TSVs in 3D ICs. ASICON (2015)
Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao
Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. PRDC (2015)
Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jian-Fei Jiang, Zhigang Mao
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2015)
Jing Guo, Liyi Xiao, Zhigang Mao
Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Zhiting Yan, Guanghui He, Xi Chen, Weifeng He, Zhigang Mao
Improved Max-Log-MAP BICM-IDD receiver for MIMO systems. IEICE Electron. Express 11 (21) (2014)
Ziyou Yao, Weifeng He, Liang Hong, Guanghui He, Zhigang Mao
Area and throughput efficient IDCT/IDST architecture for HEVC standard. ISCAS (2014)
Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao
TSVs-aware floorplanning for 3D integrated circuit. ASICON (2013)
Zheng Tang, Jing Xie, Zhigang Mao
A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design. ASICON (2013)
Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electron. Express 10 (9) (2013)
Mingyuan Ren, Xiaowei Liu, Wen Zuo, Zhigang Mao
Analysis of electromechanical interface model for liquid floated micro-gyroscope. NEMS (2013)
Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. ASICON (2013)
Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. ISCA (2013)
Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao
Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs. IEEE Micro 33 (6) (2013)
Yuxiao Ling, Zheng Guo, Zhimin Zhang, Zhigang Mao, Zeleng Zhuang
A Block Cipher Circuit Design against Power Analysis. CIS (2013)
Zhi Yue, Guanghui He, Jiangpeng Li, Jun Ma, Zhigang Mao
A soft-output parallel stack algorithm for MIMO detection. SiPS (2013)
Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
A cost effective 2-D adaptive block size IDCT architecture for HEVC standard. MWSCAS (2013)
Weiguang Sheng, Weifeng He, Jian-Fei Jiang, Zhigang Mao
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops (2012)
Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao
Contention and energy aware mapping for real-time applications on Network-on-Chip. ISOCC (2012)
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Pengfei Gou, Bing Yang, Mingyan Yu, Zhigang Mao
Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures. NAS (2012)
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL (2011)
Xin-chun Wu, Bin Zhou, Jinxiang Wang, Zhigang Mao
Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems. Wirel. Pers. Commun. 60 (2) (2011)
Yucheng Liu, Jing Xie, Zhigang Mao
A reconfigurable linear array processor architecture for data parallel and computation intensive applications. ASICON (2011)
Jianpeng Yu, Jun Ma, Zhigang Mao
Parallel SFSD MIMO detection with SOFT-HARD combination enumeration. SiPS (2011)
Xin-chun Wu, Jinxiang Wang, Bin Zhou, Zhigang Mao, Zhiqiang Gao
Companding schemes based on transforming signal statistics into trigonal distributions for PAPR reduction in OFDM systems. Int. J. Commun. Syst. 24 (6) (2011)
Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao
Robust design of sub-threshold flip-flop cells for wireless sensor network. VLSI-SoC (2011)
Jin Huang, Jing Xie, Zhigang Mao
A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications. ASICON (2011)
Jing Xie, Huimin Xing, Zhigang Mao
On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system. VLSI-SoC (2011)
Zaixiao Zheng, Zhigang Mao, Jian-Fei Jiang
An efficient 90nm technology-node GHz transceiver of on-chip global interconnect. ASICON (2011)
Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He
Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

Zhigang Mao