Jian-Fei Jiang

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 13

Top Topics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Jiaming Tu, Mengdan Lou, Jian-Fei Jiang, Dewu Shu, Guanghui He
An Efficient Massive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithm to Flexible Architecture. IEEE Trans. Circuits Syst. (11) (2020)
Yijia Zhang, Weiguang Sheng, Jian-Fei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. 12 (7) (2020)
Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jian-Fei Jiang
A New Approximate Multiplier Design for Digital Signal Processing. ASICON (2019)
Qin Wang, Zechen Liu, Jian-Fei Jiang, Naifeng Jing, Weiguang Sheng
A New Cellular-Based Redundant TSV Structure for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Taozhong Li, Qin Wang, Yongxin Zhu, Jian-Fei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jian-Fei Jiang, Jing Jin, Naifeng Jing
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. ISCAS (2019)
Xianjie Long, Qin Wang, Jian-Fei Jiang, Nin Guan
An on-chip circuit for timing measurement of SRAM IP. ASICON (2017)
Wei Jin, Weifeng He, Jian-Fei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integr. 58 (2017)
Qin Wang, Zhenyang Chen, Jian-Fei Jiang, Zheng Guo, Zhigang Mao
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. Integr. 59 (2017)
Xuwei Jin, Wei Jin, Hao Zhang, Jian-Fei Jiang, Weifeng He
A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. ISCAS (2017)
Chaoyang Li, Qin Wang, Jian-Fei Jiang, Nin Guan
A metastability-based true random number generator on FPGA. ASICON (2017)
Jian-Fei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. 25 (10) (2016)
Weiguang Sheng, Jian-Fei Jiang, Zhigang Mao
Parallel SER analysis for combinational and sequential standard cell circuits. Microelectron. J. 50 (2016)
Jiayi Hu, Qin Wang, Jian-Fei Jiang, Jing Xie, Zhigang Mao
A crosstalk avoidance scheme based on re-layout of signal TSV. ASICON (2015)
Naifeng Jing, Jiacheng Zhou, Jian-Fei Jiang, Xin Chen, Weifeng He, Zhigang Mao
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD (2015)
Jian-Fei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao
Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express 12 (8) (2015)
Jian-Fei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao
A contactless testing methodology for pre-bond interposer. MWSCAS (2015)
Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jian-Fei Jiang, Zhigang Mao
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2015)
Zhenyang Chen, Qin Wang, Jing Xie, Jin Tian, Jian-Fei Jiang, Yufei Li, Wen Yin
Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling. ISCAS (2013)
Weiguang Sheng, Weifeng He, Jian-Fei Jiang, Zhigang Mao
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops (2012)
Jian-Fei Jiang, Wei-Guang Sheng, Zhi-Gang Mao, Wei-Feng He
A pre-emphasis circuit design for high speed on-chip global interconnect. ISCAS (2012)
Zaixiao Zheng, Zhigang Mao, Jian-Fei Jiang
An efficient 90nm technology-node GHz transceiver of on-chip global interconnect. ASICON (2011)
Can Wang, Qin Wang, Jian-Fei Jiang
A new asynchronous delay-insensitive link based on a 1-of-4 LETS code. ASICON (2011)
Jian-Fei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao
A clock-less transceiver for global interconnect. VLSI-SoC (2011)
Xu Wang, Jian-Fei Jiang, Zhi-Gang Mao, Bingjing Ge, Xinglong Zhao
A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme. ICECS (2011)