A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.
Xu WangJian-Fei JiangZhi-Gang MaoBingjing GeXinglong ZhaoPublished in: ICECS (2011)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- single chip
- wireless transmission
- high power
- digital signal processing
- power reduction
- logic circuits
- nm technology
- vlsi architecture
- cmos technology
- vlsi circuits
- power management
- power saving
- signal processing
- gate array
- image processing
- energy consumption
- signal processor