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A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.

Wei JinWeifeng HeJian-Fei JiangHaichao HuangXuejun ZhaoYanan SunXin ChenNaifeng Jing
Published in: Integr. (2017)
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