Weifeng He

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 62

Top Topics

Error Detection

Energy Efficiency

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

Publications

Rui Qin, Zhifen Zhang, Jing Huang, Zhengyao Du, Xianwen Xiang, Jie Wang, Guangrui Wen, Weifeng He
A novel physically interpretable end-to-end network for stress monitoring in laser shock peening. Comput. Ind. 155 (2024)
Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jing Jin, Jun Yang, Mingoo Seok
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. IEEE J. Solid State Circuits 59 (2) (2024)
Chuxiong Lin, Weifeng He, Yanan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits 59 (2) (2024)
Xin Wu, Xiaolong Wei, Haojun Xu, Weifeng He, Liucheng Zhou, Yuanhan Hou, Yixuan Wang
Research on the Performance State Assessment of Aero-Engine Compressor Driven by Realistic Digital Aero-Engine Structure Model. IEEE Trans. Instrum. Meas. 73 (2024)
Xin Wu, Xiaolong Wei, Haojun Xu, Yuanhan Hou, Caizhi Li, Yizhen Yin, Weifeng He, Liucheng Zhou
Aeroengine Blades Damage Detection and Measurement Based on Multimodality Fusion Learning. IEEE Trans. Instrum. Meas. 73 (2024)
Qichun Hu, Xiaolong Wei, Xin Zhou, Yizhen Yin, Haojun Xu, Weifeng He, Senlin Zhu
Point cloud enhancement optimization and high-fidelity texture reconstruction methods for air material via fusion of 3D scanning and neural rendering. Expert Syst. Appl. 242 (2024)
Yanan Sun, Zhi Li, Weiyi Liu, Weifeng He, Qin Wang, Zhigang Mao
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Zhifen Zhang, Rui Qin, Geng Li, Zhengyao Du, Guangrui Wen, Weifeng He
A Novel Approach for Surface Integrity Monitoring in High-Energy Nanosecond-Pulse Laser Shock Peening: Acoustic Emission and Hybrid-Attention CNN. IEEE Trans. Ind. Informatics 19 (3) (2023)
Xin Wu, Xiaolong Wei, Haojun Xu, Caizhi Li, Yuanhan Hou, Yizhen Yin, Weifeng He
PointCNT: A One-Stage Point Cloud Registration Approach Based on Complex Network Theory. Remote. Sens. 15 (14) (2023)
Yanan Sun, Dengfeng Wang, Liukai Xu, Yiming Chen, Zhi Li, Songyuan Liu, Weifeng He, Yongpan Liu, Huazhong Yang, Xueqing Li
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (8) (2023)
Rui Qin, Zhifen Zhang, Jing Huang, Jie Wang, Zhengyao Du, Guangrui Wen, Weifeng He
Surface stress monitoring of laser shock peening using AE time-scale texture image and multi-scale blueprint separable convolutional networks with attention mechanism. Expert Syst. Appl. 224 (2023)
Dengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. ICCAD (2023)
Dengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. CoRR (2023)
Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Weifeng He
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Yuxuan Qin, Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Lin Shao, Mingche Lai, Shi Xu, Chuxiong Lin, Weifeng He
A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip. ISCAS (2023)
Jieyu Li, Weifeng He, Bo Zhang, Liang Qi, Guanghui He, Mingoo Seok
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition. ISSCC (2023)
Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (3) (2023)
Xue Yuan, Kun Su, Jingyi He, Shi Xu, Jieyu Li, Weifeng He
An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations. ISCAS (2023)
Zhifen Zhang, Rui Qin, Geng Li, Zimin Liu, Guangrui Wen, Weifeng He
Online Evaluation of Surface Hardness for Aluminum Alloy in LSP Using Modal Acoustic Emission. IEEE Trans. Instrum. Meas. 71 (2022)
Shuai Yuan, Yanan Sun, Weifeng He, Qianrong Gu, Shi Xu, Zhigang Mao, Shikui Tu
MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification. IEEE Trans. Geosci. Remote. Sens. 60 (2022)
Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption. CICC (2022)
Liukai Xu, Songyuan Liu, Zhi Li, Dengfeng Wang, Yiming Chen, Yanan Sun, Xueqing Li, Weifeng He, Shi Xu
CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration. DAC (2022)
Chuxiong Lin, Weifeng He, Yannan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation. CICC (2022)
Dengfeng Wanq, Zhi Li, Chengjun Chang, Weifeng He, Yanan Sun
All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations. ICTA (2022)
Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. DAC (2021)
Yongjie Lu, Weifeng He
A Dual-rail Based Dynamic Voltage and Frequency Scaling for Wide-Voltage-Range Processor. ASICON (2021)
Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits. ICCAD (2021)
Hao Zhang, Jieyu Li, Weifeng He, Yanan Sun, Mingoo Seok
An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM. ISCAS (2021)
Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang
Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars. ISCAS (2021)
Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Pavan Kumar Chundi, Zhigang Mao, Mingoo Seok
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits 56 (7) (2021)
Weijun Zheng, Weiping Shao, Weifeng He, Jian Zhang, Bin Hou, Yong Zhang
Hierarchical Resource Allocation for RAN slicing in Power Wireless Private Network. ICSPCC (2021)
Jieyu Li, Zihan Lian, Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process. ISCAS (2021)
Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits. ISCAS (2021)
Chao Zhang, Jingtong Mo, Zihan Lian, Weifeng He
High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory. ISCAS (2021)
Tianhong Shen, Yanan Sun, Weifeng He, Zhi Li, Weiyi Liu, Zhezhi He, Li Jiang
A Ternary Memristive Logic-in-Memory Design for Fast Data Scan. ICTA (2021)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Jing Wang, Liu Yang, Zhanqiang Huo, Weifeng He, Junwei Luo
Multi-Label Classification of Fundus Images With EfficientNet. IEEE Access 8 (2020)
Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Zhigang Mao, Mingoo Seok
25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. ISSCC (2020)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. ICEIC (2019)
Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs (5) (2019)
Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. ASICON (2019)
Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jian-Fei Jiang
A New Approximate Multiplier Design for Digital Signal Processing. ASICON (2019)
Yongjie Lu, Yanan Sun, Weifeng He, Zhigang Mao
A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. NANOARCH (2019)
Joao Pedro Cerqueira, Jieyu Li, Jiangyi Li, Weifeng He, Mingoo Seok
A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies. MWSCAS (2019)
Pengfei Ji, Jing Gao, Wenyi Xu, Yanan Sun, Weifeng He, Hui Wu
Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array. ISCAS (2018)
Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Wei Jin, Weifeng He, Jian-Fei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integr. 58 (2017)
Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
Pipelines Based on Wide-Pulsed-Latch Design Techniques. IEEE J. Solid State Circuits 52 (9) (2017)
Li Hu, Jiawei Gu, Guanghui He, Weifeng He
A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications. ISCAS (2017)
Xuwei Jin, Wei Jin, Hao Zhang, Jian-Fei Jiang, Weifeng He
A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. ISCAS (2017)
Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. ASICON (2017)
Ling Chen, Yanan Sun, Weifeng He
Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme. ASICON (2017)
Yongming Ding, Wei Jin, Guanghui He, Weifeng He
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. ASICON (2017)
Wei Jin, Guanghui He, Weifeng He, Zhigang Mao
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. Integr. 59 (2017)
Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li
A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE (2017)
Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. Microelectron. J. 62 (2017)
Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT (2016)
Zhiting Yan, Guanghui He, Weifeng He, Shuaijie Wang, Zhigang Mao
High performance parallel turbo decoder with configurable interleaving network for LTE application. Integr. 52 (2016)
Jian-Fei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. 25 (10) (2016)
Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. A-SSCC (2016)
Zhiting Yan, Guanghui He, Weifeng He, Zhigang Mao
Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2015)
Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao
Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig (2015)
Naifeng Jing, Jiacheng Zhou, Jian-Fei Jiang, Xin Chen, Weifeng He, Zhigang Mao
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD (2015)
Jian-Fei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao
Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express 12 (8) (2015)
Zijian Hou, Xin Chen, Weifeng He
Improved pipeline data flow for DySER-based platform. ISQED (2015)
Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jian-Fei Jiang, Zhigang Mao
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2015)
Fengshuo Tian, Weiguang Sheng, Weifeng He
An automatic translation and parallelization system for general purpose reconfigurable processor. ASICON (2015)
Zhiting Yan, Guanghui He, Xi Chen, Weifeng He, Zhigang Mao
Improved Max-Log-MAP BICM-IDD receiver for MIMO systems. IEICE Electron. Express 11 (21) (2014)
Ziyou Yao, Weifeng He, Liang Hong, Guanghui He, Zhigang Mao
Area and throughput efficient IDCT/IDST architecture for HEVC standard. ISCAS (2014)
Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electron. Express 10 (9) (2013)
Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. ASICON (2013)
Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
A cost effective 2-D adaptive block size IDCT architecture for HEVC standard. MWSCAS (2013)
Weiguang Sheng, Weifeng He, Jian-Fei Jiang, Zhigang Mao
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops (2012)
Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao
Contention and energy aware mapping for real-time applications on Network-on-Chip. ISOCC (2012)
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Shunqing Yan, Liang Hong, Weifeng He, Qin Wang
Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC. SITIS (2012)
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL (2011)
Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao
Robust design of sub-threshold flip-flop cells for wireless sensor network. VLSI-SoC (2011)
Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao
A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. VLSI-SoC (2011)
Li Xie, Weifeng He, Naifeng Jing, Zhigang Mao
A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. ISCAS (2011)
Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao
Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. ASICON (2011)
Yuliang Tao, Guanghui He, Weifeng He, Qin Wang, Jun Ma, Zhigang Mao
Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems. ISCAS (2011)
Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He
Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD (2011)
Naifeng Jing, Weifeng He, Zhigang Mao
A general statistical estimation for application mapping in Network-on-Chip. VLSI-SoC (2011)
Hao Wang, Weiguang Sheng, Weifeng He
Automatic compilation flow for a coarse-grained reconfigurable processor. ASICON (2011)
Naifeng Jing, Weifeng He, Zhigang Mao
Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. SoCC (2010)
Weifeng He, Weiwei Chen, Zhigang Mao
An efficient VLSI architecture for extended variable block sizes motion estimation. SoCC (2010)
Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao
Statistical estimation and evaluation for communication mapping in Network-on-Chip. Integr. 43 (2) (2010)
Weifeng He, Yunlong Bi, Zhigang Mao
Efficient frame-level pipelined array architecture for full-search block-matching motion estimation. ISCAS (3) (2005)