Sign in
Mitigating FPGA interconnect soft errors by in-place LUT inversion.
Naifeng Jing
Ju-Yueh Lee
Weifeng He
Zhigang Mao
Lei He
Published in:
ICCAD (2011)
Keyphrases
</>
high speed
hardware implementation
low cost
real time
field programmable gate array
image reconstruction
data acquisition
real time image processing
inverse halftoning
hardware architectures
verilog hdl
digital images
error detection
digital signal