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IEEE Trans. Very Large Scale Integr. Syst.
1993
2003
2013
2024
1993
2024
Keyphrases
Publications
volume 32, number 6, 2024
Yerzhan Mustafa
,
Selçuk Köse
Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Bingbing Ma
,
Wei Li
,
Hongtao Xu
Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Jongchan An
,
Seung-Myeong Yu
,
Gwangmyeong An
,
Bongsu Kim
,
Hyunsu Jang
,
Sewook Hwang
,
Junyoung Song
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Wei Xiong
,
Jiacheng Cao
,
Yaozhang Liu
,
Jian Wang
,
Jinmei Lai
,
Miaoqing Huang
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Nastaran Darabi
,
Maeesha Binte Hashem
,
Hongyi Pan
,
Ahmet Enis Çetin
,
Wilfred Gomes
,
Amit Ranjan Trivedi
ADC/DAC-Free Analog Acceleration of Deep Neural Networks With Frequency Transformation.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Tianyang Yu
,
Bi Wu
,
Ke Chen
,
Chenggang Yan
,
Weiqiang Liu
Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Hayoung Lee
,
Sooryeong Lee
,
Sungho Kang
RA-Aware Fail Data Collection Architecture for Cost Reduction.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Lingfeng Zhou
,
Shanlin Xiao
,
Huiyao Wang
,
Jinghai Wang
,
Zeyang Xu
,
Bohan Wang
,
Zhiyi Yu
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Xiao Wu
,
Miaoxin Wang
,
Jun Lin
,
Zhongfeng Wang
Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Alexandre Proulx
,
Jean-Yves Chouinard
,
Amine Miled
,
Paul Fortier
Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Robert Balas
,
Alessandro Ottaviano
,
Luca Benini
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Amit Mazumder Shuvo
,
Tao Zhang
,
Farimah Farahmandi
,
Mark M. Tehranipoor
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
Amisha Srivastava
,
Sanjay Das
,
Navnil Choudhury
,
Rafail Psiakis
,
Pedro Henrique Silva
,
Debjit Pal
,
Kanad Basu
SCAR: Power Side-Channel Analysis at RTL Level.
IEEE Trans. Very Large Scale Integr. Syst.
32 (6) (2024)
volume 32, number 7, 2024
Ziyang Kang
,
Jingwei Zhu
,
Xun Xiao
,
Shiming Li
,
Lei Wang
,
De Ma
,
Gang Pan
LSM-Based Hotspot Prediction and Hotspot-Aware Routing in NoC-Based Neuromorphic Processor.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Siji Huang
,
Debajit Basak
,
Yanhang Chen
,
Qifeng Huang
,
Yifei Fan
,
Jie Yuan
An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Shao-Chun Hung
,
Arjun Chaudhuri
,
Sanmitra Banerjee
,
Krishnendu Chakrabarty
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Haoyang Shen
,
Deepu John
,
Barry Cardiff
FEC-Aided Decision Feedback Blind Mismatch Calibration of TIADCs in Wireless Time-Varying Channel Environments.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Md Rafid Muttaki
,
Md Habibur Rahman
,
Akshay Kulkarni
,
Mark M. Tehranipoor
,
Farimah Farahmandi
FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Baoling Hong
,
Haikuo Shao
,
Zhongfeng Wang
A Low Complexity Online Learning Approximate Message Passing Detector for Massive MIMO.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Alireza Nahvy
,
Zainalabedin Navabi
Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Kashif Inayat
,
Inayat Ullah
,
Jaeyong Chung
Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Morteza Yousefloo
,
Omid Akbari
Design Exploration of Fault-Tolerant Deep Neural Networks Using Posit Number Representation System.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Behdad Jamadi
,
Shiuh-Hua Wood Chiang
,
Armin Tajalli
Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Haitong Huang
,
Cheng Liu
,
Xinghua Xue
,
Bo Liu
,
Huawei Li
,
Xiaowei Li
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Shu-Yu Chang
,
Shi-Yu Huang
A Check-and-Balance Scheme in Multiphase Delay-Locked Loop.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Zhifei Lu
,
Bowen Zhang
,
Xizhu Peng
,
Hang Liu
,
Xiaolei Ye
,
Yuzhuo Li
,
Yutao Peng
,
Yao Xiao
,
Wei Zhang
,
He Tang
A New Artificial Neural Network-Based Calibration Mechanism for ADCs: A Time-Interleaved ADC Case Study.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Florian Hirner
,
Ahmet Can Mert
,
Sujoy Sinha Roy
Proteus: A Pipelined NTT Architecture Generator.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Ashish Ranjan Shadangi
,
Suvra Sekhar Das
,
Indrajit Chakrabarti
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Yi-Hao Lan
,
Shen-Iuan Liu
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
Bowen Xia
,
De-han Wang
,
Wenhua Chen
,
Fadhel M. Ghannouchi
,
Zhenghe Feng
A 24-40-GHz Broadband Beamforming TRX Front-End IC With Unified Phase and Gain Control for Multiband Phased Array Systems.
IEEE Trans. Very Large Scale Integr. Syst.
32 (7) (2024)
volume 32, number 8, 2024
Runze Yu
,
Zhenhao Li
,
Xi Deng
,
Zhaoxu Wang
,
Wei Jia
,
Haoming Zhang
,
Zhenglin Liu
iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Luchang He
,
Chenchen Xie
,
Zhao Han
,
Qingyu Wu
,
Houpeng Chen
,
Shibing Long
,
Xi Li
,
Zhitang Song
A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Nunzio Spina
,
Marcello Raimondi
,
Alessandro Castorina
,
Egidio Ragonese
,
Giuseppe Palmisano
A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Madhan Thirumoorthi
,
Alexander J. Leigh
,
Moslem Heidarpur
,
Mitra Mirhassani
,
Mohammed A. S. Khalid
).
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Junichi Sakamoto
,
Daisuke Fujimoto
,
Riku Anzai
,
Naoki Yoshida
,
Tsutomu Matsumoto
High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Chao Li
,
Chen Sun
,
Jianyi Yang
,
Kai Ni
,
Xiao Gong
,
Cheng Zhuo
,
Xunzhao Yin
Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Zikang Zhou
,
Xuyang Duan
,
Jun Han
A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Yi-Fan Liu
,
Dawei Wang
,
Zhekang Dong
,
Hao Xie
,
Wen-Sheng Zhao
Implementation of Multiple-Step Quantized STDP Based on Novel Memristive Synapses.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
D. R. Vasanthi
,
Sanampudi Gopala Krishna Reddy
,
Madhav Rao
) Polynomial.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Shouharda Ghosh
,
Pramod Kumar Meher
,
Dwaipayan Ray
,
Nithin V. George
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Loai G. Salem
Symmetric and Multiphase-Interleaved Ladder Bucks for DC Capacitors Elimination.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Jhe-En Lin
,
Yi-Hao Lan
,
Shen-Iuan Liu
A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Seyedarmin Azizi
,
Mahdi Nazemi
,
Mehdi Kamal
,
Massoud Pedram
Low-Precision Mixed-Computation Models for Inference on Edge.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Xiaolu Hou
,
Jakub Breier
,
Mladen Kovacevic
Another Look at Side-Channel-Resistant Encoding Schemes.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Zijian Tang
,
Yongxiang Guo
,
Minqian Zheng
,
Chao Sun
,
Yusong Wu
,
Runjiu Fang
,
Ying Fang
,
Milin Zhang
An 112-Ch Neural Signal Acquisition SoC With Full-Channel Read-Out and Processing Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
M. Vafaieenezhad
,
M. B. Ghaznavi-Ghoushchi
An Unconditional Evenly Spaced STRO With a New Mitigated Drafting Effect Muller C-Element.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Enlai Li
,
Sharad Sinha
,
Wei Zhang
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Xu Yan
,
Jingyuan Zhang
,
Guansheng Lv
,
Wenhua Chen
,
Yongxin Guo
Gain and Power Enhancement With Coupled Technique for a Distributed Power Amplifier in 0.25- μm GaN HEMT Technology.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Jonti Talukdar
,
Woohyun Paik
,
Eduardo Ortega
,
Krishnendu Chakrabarty
ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse Engineering.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)
Fanny Spagnolo
,
Stefania Perri
,
Massimo Vatalaro
,
Fabio Frustaci
,
Felice Crupi
,
Pasquale Corsonello
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization.
IEEE Trans. Very Large Scale Integr. Syst.
32 (8) (2024)