Pramod Kumar Meher

ORCID

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 43

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

ISCAS

Circuits Syst. Signal Process.

Publications

Anil Kali, Samrat L. Sabat, Pramod Kumar Meher
A Novel DA-Based Parallel Architecture for Inner-Product of Variable Vectors. ISCAS (2024)
Mohammed Yusuf Ansari, Iffa Afsa Changaai Mangalote, Pramod Kumar Meher, Omar Aboumarzouk, Abdulla Al-Ansari, Osama Halabi, Sarada Prasad Dakua
Advancements in Deep Learning for B-Mode Ultrasound Segmentation: A Comprehensive Review. IEEE Trans. Emerg. Top. Comput. Intell. 8 (3) (2024)
Shouharda Ghosh, Pramod Kumar Meher, Dwaipayan Ray, Nithin V. George
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments. IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Srikant Kumar Beura, Bishnulatpam Pushpa Devi, Prabir Saha, Pramod Kumar Meher
Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers. Circuits Syst. Signal Process. 43 (6) (2024)
Anu Verma, Khyati Kiyawat, Bishnu Prasad Das, Pramod Kumar Meher
An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation. IEEE Trans. Very Large Scale Integr. Syst. 31 (8) (2023)
Mohammed Yusuf Ansari, Yin Yang, Pramod Kumar Meher, Sarada Prasad Dakua
Dense-PSP-UNet: A neural network for fast inference liver ultrasound segmentation. Comput. Biol. Medicine 153 (2023)
Anil Kali, Samrat L. Sabat, Pramod Kumar Meher
Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors. IEEE Trans. Very Large Scale Integr. Syst. 31 (9) (2023)
Sun Sik Lee, Thanh Dat Nguyen, Pramod Kumar Meher, Sang Yoon Park
Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design. IEEE Access 10 (2022)
Supriya Aggarwal, Pramod Kumar Meher
Enhanced Sharpening of CIC Decimation Filters, Implementation and Applications. Circuits Syst. Signal Process. 41 (8) (2022)
Su Min Cho, Pramod Kumar Meher, Luong Tran Nhat Trung, Hyo Jin Cho, Sang Yoon Park
Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis. IEEE Access 9 (2021)
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
An Analytical Framework and Approximation Strategy for Efficient Implementation of Distributed Arithmetic-Based Inner-Product Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Basant Kumar Mohanty, Pramod Kumar Meher
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Maher Jridi, Ayman Alfalou, Pramod Kumar Meher
Efficient approximate core transform and its reconfigurable architectures for HEVC. J. Real Time Image Process. 17 (2) (2020)
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
Analysis and Design of Approximate Inner-Product Architectures Based on Distributed Arithmetic. ISCAS (2019)
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher
) using Toeplitz Matrix-Vector Product Method. ISCAS (2019)
Subhendu Kumar Sahoo, Pramod Kumar Meher, G. Ganesh Ganjikunta
Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation. IEEE Consumer Electron. Mag. 8 (3) (2019)
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Sumit Satyavijay Wadkar, Bishnu Prasad Das, Pramod Kumar Meher
Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series. iSES (2019)
G. Ganesh Kumar, Subhendu Kumar Sahoo, Pramod Kumar Meher
50 Years of FFT Algorithms and Applications. Circuits Syst. Signal Process. 38 (12) (2019)
Basant K. Mohanty, Pramod Kumar Meher
Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Bimal Kumar Meher, Pramod Kumar Meher
Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields. Circuits Syst. Signal Process. 38 (2) (2019)
Syed Naveen Altaf Ahmed, Pramod Kumar Meher, Achutavarrier Prasad Vinod
Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication Systems. Circuits Syst. Signal Process. 37 (6) (2018)
Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher
Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Bhavan A. Jasani, Siew-Kei Lam, Pramod Kumar Meher, Meiqing Wu
Threshold-Guided Design and Optimization for Harris Corner Detector Architecture. IEEE Trans. Circuits Syst. Video Technol. 28 (12) (2018)
Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee
) Based on Trinomials. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Jiafeng Xie, Pramod Kumar Meher, Mingui Sun, Yuecheng Li, Bo Zeng, Zhi-Hong Mao
) Based on NIST Polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Subhendu Kumar Sahoo, Pramod Kumar Meher
Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio. iNIS (2017)
Xin Lou, Pramod Kumar Meher, Yajun Yu, Wenbin Ye
Novel Structure for Area-Efficient Implementation of FIR Filters. IEEE Trans. Circuits Syst. II Express Briefs (10) (2017)
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (2) (2017)
Pramod Kumar Meher, Xin Lou
) Based on Irreducible All-One Polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Maher Jridi, Pramod Kumar Meher
Scalable Approximate DCT Architectures for Efficient HEVC-Compliant Video Coding. IEEE Trans. Circuits Syst. Video Technol. 27 (8) (2017)
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
Concept, Design, and Implementation of Reconfigurable CORDIC. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Nikolaos V. Boulgouris, David R. Bull, Marco Cagnazzo, Andrea Cavallaro, Gene Cheung, Amit K. Roy-Chowdhury, Pedro Comesaña Alfaro, Shan Du, Sarp Ertürk, Markus Flierl, Gian Luca Foresti, Gang Hua, Zhu Li, Weisi Lin, Siwei Ma, Pramod Kumar Meher, Debargha Mukherjee, Aleksandra Pizurica, Andrea Prati, Paolo Remagnino, Arun Ross, Shin'ichi Satoh, Andreas E. Savakis, Heiko Schwarz, Ling Shao, Shervin Shirmohammadi, Giuseppe Valenzise, Meng Wang, Zhou Wang, Yonggang Wen, Dong Xu, Junsong Yuan, Yuan Yuan
Introduction of New Associate Editors. IEEE Trans. Circuits Syst. Video Technol. 26 (2) (2016)
Basant Kumar Mohanty, Pramod Kumar Meher
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Pramod Kumar Meher
Seamless Pipelining of DSP Circuits. Circuits Syst. Signal Process. 35 (4) (2016)
Chiou-Yng Lee, Pramod Kumar Meher
) Using Generalized (a, b)-Way Karatsuba Algorithm". IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Pramod Kumar Meher
On Efficient Retiming of Fixed-Point Circuits. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Basant Kumar Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal, M. N. S. Swamy
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. Integr. 54 (2016)
Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. IEEE Trans. Very Large Scale Integr. Syst. 24 (7) (2016)
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2016)
Hassan Rabah, Abbes Amira, Basant Kumar Mohanty, Somaya Al-Máadeed, Pramod Kumar Meher
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Chiou-Yng Lee, Pramod Kumar Meher
) Using Symmetric TMVP and Block Recombination Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
Maher Jridi, Ayman Alfalou, Pramod Kumar Meher
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
) for NIST Recommended Pentanomials. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
) Based on Irreducible Trinomials. IEEE Trans. Circuits Syst. II Express Briefs (5) (2015)
Xin Lou, Pramod Kumar Meher, Ya Jun Yu
Fine-grained pipelining for multiple constant multiplications. ISCAS (2015)
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Chiou-Yng Lee, Pramod Kumar Meher
) Using Generalized (a, b)-Way Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2015)
Basant K. Mohanty, Pramod Kumar Meher, Thambipillai Srikanthan
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. ISCAS (2015)
Pramod Kumar Meher, Basant Kumar Mohanty, M. N. S. Swamy
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters. VLSI Design (2015)
Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2015)
Jeng-Shyang Pan, Pramod Kumar Meher, Chiou-Yng Lee, Hong-Hai Bai
). ISCAS (2015)
Chiou-Yng Lee, Pramod Kumar Meher
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs (5) (2015)
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2015)
Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. ISIC (2014)
Pramod Kumar Meher, Sang Yoon Park, Basant Kumar Mohanty, Khoon Seong Lim, Chuohao Yeo
Efficient Integer DCT Architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. 24 (1) (2014)
Pramod Kumar Meher, Basant K. Mohanty, Thambipillai Srikanthan
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. ISCAS (2014)
Pramod Kumar Meher, Sang Yoon Park
Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2014)
Pramod Kumar Meher, Sang Yoon Park
A novel DA-based architecture for efficient computation of inner-product of variable vectors. ISCAS (2014)
Supriya Aggarwal, Pramod Kumar Meher
Reconfigurable CORDIC architectures for multi-mode and multi-trajectory operations. ISCAS (2014)
Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Chiou-Yng Lee, Pramod Kumar Meher, Chien-Ping Chang
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Xin Lou, Ya Jun Yu, Pramod Kumar Meher
High-speed multiplier block design based on bit-level critical path optimization. ISCAS (2014)
Sang Yoon Park, Pramod Kumar Meher
Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter. IEEE Trans. Circuits Syst. II Express Briefs (7) (2014)
Basant K. Mohanty, Pramod Kumar Meher, Somaya Al-Máadeed, Abbes Amira
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Pramod Kumar Meher, Sang Yoon Park
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay. IEEE Trans. Very Large Scale Integr. Syst. 22 (2) (2014)
Basant K. Mohanty, Pramod Kumar Meher
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation. IET Image Process. 8 (6) (2014)
Yu Pan, Pramod Kumar Meher
Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2014)
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
) Based on All-One Polynomials. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Basant K. Mohanty, Pramod Kumar Meher
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm. IEEE Trans. Signal Process. 61 (4) (2013)
Soni Prattipati, M. N. S. Swamy, Pramod Kumar Meher
A variable quantization technique for image compression using integer Tchebichef transform. ICICS (2013)
Bimal Kumar Meher, Pramod Kumar Meher
) Generated by Trinomials. Circuits Syst. Signal Process. 32 (6) (2013)
Pramod Kumar Meher, Sang Yoon Park
CORDIC Designs for Fixed Angle of Rotation. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Natarajan Sudha, Niladri B. Puhan, Pramod Kumar Meher
Special section on image and video processing for security. Signal Image Video Process. 7 (4) (2013)
Jiafeng Xie, Jianjun He, Pramod Kumar Meher
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic. IEEE Trans. Computers 62 (6) (2013)
Soni Prattipati, Sujata Ishwar, M. N. S. Swamy, Pramod Kumar Meher
A fast 8×8 integer Tchebichef transform and comparison with integer cosine transform for image compression. MWSCAS (2013)
Sang Yoon Park, Pramod Kumar Meher
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic. IEEE Trans. Circuits Syst. II Express Briefs (6) (2013)
Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2013)
Basant K. Mohanty, Pramod Kumar Meher
Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT. IEEE Trans. Circuits Syst. Video Technol. 23 (2) (2013)
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2013)
Maher Jridi, Pramod Kumar Meher, Ayman Alfalou
Zero-quantised discrete cosine transform coefficients prediction technique for intra-frame video encoding. IET Image Process. 7 (2) (2013)
Sang Yoon Park, Pramod Kumar Meher
Flexible integer DCT architectures for HEVC. ISCAS (2013)
Pramod Kumar Meher, Saraju P. Mohanty, A. Prasad Vinod
Guest Editorial: Advanced Techniques for Efficient Electronic System Design. Circuits Syst. Signal Process. 32 (6) (2013)
Basant K. Mohanty, Anurag Mahajan, Pramod Kumar Meher
Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT. IEEE Trans. Circuits Syst. II Express Briefs (7) (2012)
Jayakishan Meher, Pramod Kumar Meher, Gananath Dash, Mukesh Kumar Raval
New encoded single-indicator sequences based on physico-chemical parameters for efficient exon identification. Int. J. Bioinform. Res. Appl. 8 (1/2) (2012)
Syed Naveen Altaf Ahmed, Pramod Kumar Meher, A. Prasad Vinod
A low-complexity spectrum sensing technique for cognitive radios based on correlation of intra-segment decimated vectors. ICCS (2012)
Basant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. ISCAS (2012)
Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012)
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
) for a wider class of trinomials using parallel register sharing. ISCAS (2012)
Maher Jridi, Ayman Alfalou, Pramod Kumar Meher
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression. VLSI Design 2012 (2012)
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Pramod Kumar Meher, Megha Maheshwari
A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm. ISCAS (2011)
Yu Pan, Pramod Kumar Meher
Efficient coefficient partitioning for decomposed DA-based inner-product computation. ISCAS (2011)

Pramod Kumar Meher.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Pramod Kumar Meher