Subhendu Kumar Sahoo

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 16

Top Topics

Reverse Engineer

Fast Fourier Transform

Random Number Generator

Top Venues

IET Circuits Devices Syst.

Int. J. Circuit Theory Appl.

IET Comput. Digit. Tech.

Publications

Apurva Kumari, Subhendu Kumar Sahoo
A new fast and efficient dehazing and defogging algorithm for single remote sensing images. Signal Process. 215 (2024)
Apurva Kumari, Subhendu Kumar Sahoo, M. C. Chinnaiah
Fast and Efficient Visibility Restoration Technique for Single Image Dehazing and Defogging. IEEE Access 9 (2021)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. Int. J. Circuit Theory Appl. 49 (8) (2021)
Ganesh Kumar Ganjikunta, Subhendu Kumar Sahoo
Power-efficient compensation circuit for fixed-width multipliers. IET Circuits Devices Syst. 14 (4) (2020)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. Int. J. Circuit Theory Appl. 48 (4) (2020)
Ganesh Kumar Ganjikunta, Subhendu Kumar Sahoo
Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g. IET Comput. Digit. Tech. 14 (5) (2020)
Aditya Japa, Palagani Yellappa, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET. ISCAS (2020)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. IET Circuits Devices Syst. 14 (5) (2020)
Subhendu Kumar Sahoo, Pramod Kumar Meher, G. Ganesh Ganjikunta
Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation. IEEE Consumer Electron. Mag. 8 (3) (2019)
G. Ganesh Kumar, Subhendu Kumar Sahoo, Pramod Kumar Meher
50 Years of FFT Algorithms and Applications. Circuits Syst. Signal Process. 38 (12) (2019)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. IET Circuits Devices Syst. 13 (5) (2019)
Subhendu Kumar Sahoo, Krishna Dhoot, Rasmita Sahoo
High Performance Ternary Multiplier Using CNTFET. ISVLSI (2018)
Ganesh Kumar Ganjikunta, Subhendu Kumar Sahoo
An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications. Integr. 57 (2017)
Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo
Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET. iNIS (2017)
Subhendu Kumar Sahoo, Pramod Kumar Meher
Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio. iNIS (2017)
G. Ganesh Kumar, Subhendu Kumar Sahoo
Implementation of a high speed multiplier for high-performance and low power applications. VDAT (2015)
Subhendu Kumar Sahoo, Anu Gupta, Abhijit R. Asati, Chandra Shekhar
A Novel Redundant Binary Number to Natural Binary Number Converter. J. Signal Process. Syst. 59 (3) (2010)
Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati, Anu Gupta
Dual channel addition based FFT processor architecture for signal and image processing. Int. J. High Perform. Syst. Archit. 2 (1) (2009)
Ashutosh Mehra, Anu Gupta, Sharvil Patil, Abhishek Mehra, Subhendu Kumar Sahoo
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers. ARTCom (2009)
Abhijit R. Asati, Subhendu Kumar Sahoo, Chandra Shekhar
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load. ICETET (2009)
Subhendu Kumar Sahoo, Abhijit Ashati, Rasmita Sahoo, Chandra Shekhar
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic. ICETET (2008)