Ramesh Vaddi

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 26

Top Topics

Reverse Engineer

Top Venues

Microelectron. J.

IET Circuits Devices Syst.

Publications

Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi
Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices. ISCAS (2024)
Vinod Kumar Ancha, Fadi N. Sibai, Venkateswarlu Gonuguntla, Ramesh Vaddi
Utilizing YOLO Models for Real-World Scenarios: Assessing Novel Mixed Defect Detection Dataset in PCBs. IEEE Access 12 (2024)
Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi
A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks. Microelectron. J. 139 (2023)
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. Microelectron. J. 133 (2023)
Santosh Kumar, Rishab Nagar, Saumya Bhatnagar, Ramesh Vaddi, Sachin Kumar Gupta, Mamoon Rashid, Ali Kashif Bashir, Tamim Alkhalifah
Chest X ray and cough sample based deep learning framework for accurate diagnosis of COVID-19. Comput. Electr. Eng. 103 (2022)
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
Negative capacitance FETs for energy efficient and hardware secure logic designs. Microelectron. J. 119 (2022)
Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi
Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks. iSES (2022)
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
Steep Switching NCFET based Logic for Future Energy Efficient Electronics. iSES (2021)
Varanasi Koundinya, Madanu Karun Chand, Dharmavarapu Dhushyanth, Devarajugattu Jayanth Saikumar, Arumalla Varun Sai, Venu Birudu, Ramesh Vaddi
Design and Analysis of 4-bit and 5-bit Flash ADC's in 90nm CMOS Technology for Energy Efficient IoT Applications. iSES (2021)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. Int. J. Circuit Theory Appl. 49 (8) (2021)
P. L. Lahari, Siva Sankar Yellampalli, Ramesh Vaddi
Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators. iSES (2021)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. Int. J. Circuit Theory Appl. 48 (4) (2020)
Aditya Japa, Palagani Yellappa, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET. ISCAS (2020)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. IET Circuits Devices Syst. 14 (5) (2020)
Nhut-Minh Ho, Ramesh Vaddi, Weng-Fai Wong
Multi-objective Precision Optimization of Deep Neural Networks for Edge Devices. DATE (2019)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. IET Circuits Devices Syst. 13 (5) (2019)
Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma, Palagani Yellappa, Jun Rim Choi, Ramesh Vaddi
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. ISCAS (2018)
Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi
Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD. J. Circuits Syst. Comput. 27 (3) (2018)
Gauri Punekar, Venkateswarlu Gonuguntla, Palagani Yellappa, Jun Rim Choi, Ramesh Vaddi
A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier. ISOCC (2018)
Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi
A low voltage capacitor based current controlled sense amplifier for input offset compensation. ISOCC (2017)
Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi
Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics. VDAT (2017)
T. Nagateja, Ramesh Vaddi
Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs. ISOCC (2017)
Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi
Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs. VDAT (2017)
Aditya Japa, T. Nagateja, Ramesh Vaddi
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms. iNIS (2017)
Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing. VLSI Design (2016)
Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi
Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. IET Circuits Devices Syst. 10 (6) (2016)
Huichu Liu, Xueqing Li, Ramesh Vaddi, Kaisheng Ma, Suman Datta, Vijaykrishnan Narayanan
Tunnel FET RF Rectifier Design for Energy Harvesting Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (4) (2014)
Kasturi Subramanyam, Sadulla Shaik, Ramesh Vaddi
Tunnel FET based low voltage static vs dynamic logic families for energy efficiency. VDAT (2014)
Huichu Liu, Ramesh Vaddi, Suman Datta, Vijaykrishnan Narayanan
Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier. ISLPED (2013)
Ramesh Vaddi, R. P. Agarwal, Sudeb Dasgupta
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options. Microelectron. J. 42 (5) (2011)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. ISVLSI (2011)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. J. Low Power Electron. 6 (1) (2010)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. Microelectron. J. 41 (4) (2010)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic. IET Circuits Devices Syst. 4 (6) (2010)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications. VLSI Design 2009 (2009)