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Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.

Aditya JapaManoj Kumar MajumderSubhendu Kumar SahooRamesh Vaddi
Published in: Int. J. Circuit Theory Appl. (2020)
Keyphrases
  • circuit design
  • digital circuits
  • design automation
  • high speed
  • power consumption
  • information leakage
  • chip design
  • simulation model
  • highly efficient
  • security issues
  • sensitive data
  • power distribution