Manoj Kumar Majumder

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 17

Top Topics

Fingerprint Authentication

Reverse Engineer

Integrated Circuit

Top Venues

IET Circuits Devices Syst.

Int. J. Circuit Theory Appl.

Publications

Nidhee Bhuwal, Kamal Solanki, Manoj Kumar Majumder, Deepika Gupta
Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA. VLSID (2024)
Shivangi Chandrakar, Deepika Gupta, Manoj Kumar Majumder
Crosstalk and Power Analysis in Tapered based Composite Cu-CNT TSV in 3D IC. ISCAS (2024)
Nidhee Bhuwal, Manoj Kumar Majumder, Deepika Gupta
Implementation of Floating Charged Memristor Emulator utilizing DVCCTA. ISCAS (2024)
Vandana Kumari, Maya Chandrakar, Manoj Kumar Majumder
Performance Analysis of Cylindrical Through Silicon Via with Interfacial Crack. ISQED (2023)
Shivangi Chandrakar, Kunal Kranti Das, Deepika Gupta, Manoj Kumar Majumder
Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV. VDAT (2022)
Shivangi Chandrakar, Deepika Gupta, Manoj Kumar Majumder
Role of Through Silicon Via in 3D Integration: Impact on Delay and Power. J. Circuits Syst. Comput. 30 (3) (2021)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. Int. J. Circuit Theory Appl. 49 (8) (2021)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. Int. J. Circuit Theory Appl. 48 (4) (2020)
Chopali Chanchal Sahu, Shivangi Chandrakar, Manoj Kumar Majumder
Signal Transmission and Reflection Losses of Cylindrical and Tapered shaped TSV in 3D Integrated Circuits. iSES (2020)
Aditya Japa, Palagani Yellappa, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET. ISCAS (2020)
Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder
Performance analysis of mixed CNT bundle interconnects at 10 nm technology. IET Circuits Devices Syst. 14 (7) (2020)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. IET Circuits Devices Syst. 14 (5) (2020)
Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder
Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects. VDAT (2019)
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. IET Circuits Devices Syst. 13 (5) (2019)
Arushi Shrivastava, Parul Damahe, Vijay Rao Kumbhare, Manoj Kumar Majumder
Designing SRAM Using CMOS and CNTFET at 32 nm Technology. iSES (2019)
Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, Shrivishal Tripathi, Manoj Kumar Majumder
An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits. VDAT (2019)
Balkrishna Choubey, Vijay Rao Kumbhare, Manoj Kumar Majumder
Performance Analysis of Graphene Based Optical Interconnect at Nanoscale Technology. VDAT (2018)
Manoj Kumar Majumder, Pankaj Kumar Das, Vobulapuram Ramesh Kumar, Brajesh Kumar Kaushik
Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect. J. Circuits Syst. Comput. 24 (10) (2015)
Manoj Kumar Majumder, Pankaj Kumar Das, Brajesh Kumar Kaushik
Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects. Microelectron. Reliab. 54 (11) (2014)
Jainender Kumar, Manoj Kumar Majumder, Brajesh Kumar Kaushik, Sudeb Dasgupta
Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations. VDAT (2013)
Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects. RAIT (2012)
Baljit Kaur, Manoj Kumar Majumder
Novel VLSI architecture for two-dimensional radon transform computations. RAIT (2012)
Naveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur, Manoj Kumar Majumder
Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET. VDAT (2012)
Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder
Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects. VDAT (2012)
Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects. ISQED (2012)
Pankaj Kumar Das, Manoj Kumar Majumder, Brajesh Kumar Kaushik, S. K. Manhas
Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects. SocProS (2012)