Sudeb Dasgupta

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 40

Top Topics

Spatial Derivatives

Design Methodology

Kolmogorov Smirnov

Top Venues

Publications

Jyoti Patel, Sankalp Rai, Vivek Kumar, Sudeb Dasgupta
Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application. ISCAS (2024)
Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. ISQED (2024)
Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta
An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. AICAS (2024)
Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. ISQED (2024)
Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS (2024)
Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS (2024)
Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED (2024)
Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu
Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. IEEE Trans. Circuits Syst. II Express Briefs 71 (6) (2024)
Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS (2023)
Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID (2023)
Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. APCCAS (2023)
Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations. Microelectron. J. 142 (2023)
Jyoti Patel, Govind Sharma, Chitraja Rajan, Vivek Kumar, Sudeb Dasgupta
Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET. APCCAS (2023)
Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS (2023)
Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD (2023)
Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta
Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. VLSID (2023)
Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta
FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. VLSID (2023)
Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS (2022)
Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Nitanshu Chauhan, Chirag Garg, Kai Ni, Amit Kumar Behera, Sarita Yadav, Shashank Banchhor, Navjeet Bagga, Avirup Dasgupta, Arnab Datta, Sudeb Dasgupta, Anand Bulusu
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI. IRPS (2022)
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. ISCAS (2022)
Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID (2022)
Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta
FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet. VDAT (2022)
Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 (2022)
Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. VDAT (2022)
Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. ISCAS (2021)
Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED (2021)
Ashutosh Yadav, Anand Bulusu, Sudeb Dasgupta, Surinder Singh
Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm. ICM (2021)
Neeraj Mishra, Lalit Dani, Kunal Sanvaniya, Sudeb Dasgupta, S. Chakraborty, Anand Bulusu
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals. IEEE Trans. Circuits Syst. (11) (2020)
Sudip Roy, Brajesh Kumar Kaushik, Sudeb Dasgupta
Selected Articles from VDAT 2017 Conference. J. Low Power Electron. 14 (2) (2018)
Sarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain
Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases. VLSI Design (2016)
Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSI Design (2016)
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. Microelectron. J. 55 (2016)
Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung
Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectron. J. 46 (12) (2015)
Ashish Joshi, S. K. Manhas, Satinder K. Sharma, Sudeb Dasgupta
An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications. Microelectron. J. 46 (6) (2015)
Sudeb Dasgupta, Bulusu Anand
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges. VLSI Design (2015)
Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand
Efficient static D-latch standard cell characterization using a novel setup time model. ISQED (2015)
Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT (2015)
Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSI Design (2014)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design. Microelectron. Reliab. 53 (5) (2013)
Pankaj Kr. Pal, Brajesh Kumar Kaushik, Sudeb Dasgupta
Spacers. VDAT (2013)
Menka Yadav, Anand Bulusu, Sudeb Dasgupta
Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. Microelectron. J. 44 (12) (2013)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices. Microelectron. Reliab. 53 (3) (2013)
Surabhi Singh, Brajesh Kumar Kaushik, Sudeb Dasgupta
in CMOS VLSI Circuits. VDAT (2013)
Jainender Kumar, Manoj Kumar Majumder, Brajesh Kumar Kaushik, Sudeb Dasgupta
Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations. VDAT (2013)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance. VDAT (2012)
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. VDAT (2012)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues. ISED (2012)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. ISQED (2012)
Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand
An accurate current source model for CMOS based combinational logic cell. ISQED (2012)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity. J. Circuits Syst. Comput. 21 (4) (2012)
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
Impact of dual-k spacer on analog performance of underlap FinFET. Microelectron. J. 43 (11) (2012)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients. IET Circuits Devices Syst. 6 (4) (2012)
Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta
) symmetric double gate MOSFET. Microelectron. J. 42 (5) (2011)
Ramesh Vaddi, R. P. Agarwal, Sudeb Dasgupta
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options. Microelectron. J. 42 (5) (2011)
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. SocProS (2) (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact. IET Circuits Devices Syst. 5 (1) (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier. Microelectron. Reliab. 51 (4) (2011)
Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. J. Low Power Electron. 7 (2) (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation. Microelectron. J. 42 (1) (2011)
Arnab Kumar Biswas, Anand Bulusu, Sudeb Dasgupta
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. ISVLSI (2011)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. ISVLSI (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
A proposed DG-FinFET based SRAM cell design with RadHard capabilities. Microelectron. Reliab. 50 (8) (2010)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. J. Low Power Electron. 6 (4) (2010)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. J. Low Power Electron. 6 (1) (2010)
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach. EMS (2010)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. Microelectron. J. 41 (4) (2010)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic. IET Circuits Devices Syst. 4 (6) (2010)
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications. VLSI Design 2009 (2009)
Y. K. Sudharshan, D. Sreenu, Ashok K. Saxena, Sudeb Dasgupta
Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study. J. Low Power Electron. 5 (1) (2009)
Maruthi Chandrasekhar Bh, Sudeb Dasgupta
A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications. ISQED (2009)
Deblina Sarkar, Deepanjan Datta, Sudeb Dasgupta
Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design. J. Comput. 3 (2) (2008)
Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. VLSI Design (2007)
Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta
Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET. Microelectron. J. 37 (6) (2006)