FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor.

Vivek Kumar Jyoti Patel Arnab Datta Sudeb Dasgupta

Published in: VLSID (2023)

Keyphrases

leakage current
high speed
metal oxide semiconductor
finite element
website
case study
modeling method
neural network
three dimensional
low power
boundary conditions
integrated circuit
cmos technology
finite element methods
nm technology