Sandeep Miryala

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 10

Top Topics

Schottky Barrier

Charge Coupled Devices

Expressive Power

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID (2023)
Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS (2022)
Sandeep Miryala, Md. Adnan Zaman, Sandeep Mittal, Yihui Ren, Grzegorz Deptuch, Gabriella Carini, Sioan Zohar, Shinjae Yoo, Jack Fried, Jin Huang, Srinivas Katkoori
Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications. ISQED (2022)
Sandeep Miryala, Gabriella Carini, Grzegorz Deptuch, Jin Huang, Srinivas Katkoori, Piotr Maj, Soumyajit Mandal, Yihui Ren, Md. Adnan Zaman
Design and Challenges of Edge Computing ASICs on Front-End Electronics. ISQED (2022)
Dominik Gorni, Grzegorz Deptuch, Sandeep Miryala
Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array. PRIME (2022)
Liang Fang, Xianshan Wen, Tao Fu, Guanhua Wang, Sandeep Miryala, Tiehui Ted Liu, Ping Gui
in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Vamshi Manthena, Sandeep Miryala, Grzegorz Deptuch, Gabriella Carini
A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process. UEMCON (2020)
Sayed Ali Seif Kashani, Hossein Karimiyan Alidash, Sandeep Miryala
Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch. IET Circuits Devices Syst. 11 (6) (2017)
Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu
A novel energy-efficient self-correcting methodology employing INWE. SMACD (2016)
Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. ACM Great Lakes Symposium on VLSI (2015)
Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI (2015)
Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems 39 (8) (2015)
Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. 45 (5) (2014)
Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera, Enrico Macii, Massimo Poncino
Modeling of Physical Defects in PN Junction Based Graphene Devices. J. Electron. Test. 30 (3) (2014)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. DSD (2014)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino, Letícia Maria Veiras Bolzani Poehls
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. LATW (2013)
Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. ISQED (2013)
Sandeep Miryala, Andrea Calimera, Massimo Poncino, Enrico Macii
Exploration of different implementation styles for graphene-based reconfigurable gates. ICICDT (2013)
Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. DATE (2013)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Power modeling and characterization of Graphene-based logic gates. PATMOS (2013)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Delay model for reconfigurable logic gates based on graphene PN-junctions. ACM Great Lakes Symposium on VLSI (2013)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
IR-drop analysis of graphene-based power distribution networks. DATE (2012)
Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI (2012)
Sandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas
Efficient nanoscale VLSI standard cell library characterization using a novel delay model. ISQED (2011)