Andrea Calimera

ORCID

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 75

Top Venues

CoRR

VLSI-SoC

DATE

VLSI-SoC (Selected Papers)

Publications

Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii, Paolo Montuschi
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning. IEEE Internet Things J. 11 (4) (2024)
Matteo Grimaldi, Luca Mocerino, Antonio Cipolletta, Andrea Calimera
Dynamic ConvNets on Tiny Devices via Nested Sparsity. IEEE Internet Things J. 10 (6, March 15) (2023)
Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Efficient Deep Learning Models for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays. IEEE Internet Things J. 10 (15) (2023)
Chen Xie, Alessio Burrello, Francesco Daghero, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference. Sensors 23 (4) (2023)
Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
Communication-Efficient Federated Learning With Gradual Layer Freezing. IEEE Embed. Syst. Lett. 15 (1) (2023)
Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services. ISLPED (2023)
Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays. CoRR (2023)
Giacomo Zema, Valentino Peluso, Andrea Calimera, Enrico Macii
Concurrent Pipeline Stages Optimization for Embedded Keyword Spotting. AIIoT (2023)
Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino
Ultra-compact Binary Neural Networks for Human Activity Recognition on RISC-V Processors. CoRR (2022)
Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. CoRR (2022)
Francesco Daghero, Alessio Burrello, Chen Xie, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 21 (4) (2022)
Chen Xie, Daniele Jahier Pagliari, Andrea Calimera
Energy-efficient and Privacy-aware Social Distance Monitoring with Low-resolution Infrared Sensors and Adaptive Inference. CoRR (2022)
Giovanni Luca Masala, Massimo Esposito, Umberto Maniscalco, Andrea Calimera
Editorial: Language and Vision in Robotics: Emerging Neural and On-Device Approaches. Frontiers Comput. Sci. 4 (2022)
Khaled Sidahmed Sidahmed Alamin, Yukai Chen, Sebastiano Gaiardelli, Stefano Spellini, Andrea Calimera, Alessandro Beghi, Gian Antonio Susto, Franco Fummi, Enrico Macii, Sara Vinco
SMART-IC: Smart Monitoring and Production Optimization for Zero-waste Semiconductor Manufacturing. LATS (2022)
Antonio Cipolletta, Valentino Peluso, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs. IEEE Internet Things J. 9 (1) (2022)
Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. CoRR (2022)
Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
Monocular Depth Perception on Microcontrollers for Edge Applications. IEEE Trans. Circuits Syst. Video Technol. 32 (3) (2022)
Chen Xie, Daniele Jahier Pagliari, Andrea Calimera
Energy-efficient and Privacy-aware Social Distance Monitoring with Low-resolution Infrared Sensors and Adaptive Inference. PRIME (2022)
Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. ISCAS (2022)
Matteo Grimaldi, Luca Mocerino, Antonio Cipolletta, Andrea Calimera
Dynamic ConvNets on Tiny Devices via Nested Sparsity. CoRR (2022)
Francesco Daghero, Alessio Burrello, Chen Xie, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks. CoRR (2022)
Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
Adaptive Test-Time Augmentation for Low-Power CPU. CoRR (2021)
Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers. VLSI-SoC (Selected Papers) (2021)
Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets. VLSI-SoC (Selected Papers) (2021)
Chen Xie, Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino
C. ISLPED (2021)
Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. VLSI-SoC (2021)
Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets. VLSI-SoC (2021)
Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino
Ultra-compact binary neural networks for human activity recognition on RISC-V processors. CF (2021)
Luca Mocerino, Andrea Calimera
Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net). IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Tania Cerquitelli, Daniele Jahier Pagliari, Andrea Calimera, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Massimo Poncino
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools. Proc. IEEE 109 (4) (2021)
Antonio Cipolletta, Andrea Calimera
Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks. DATE (2021)
Antonio Cipolletta, Andrea Calimera
On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage. DAC (2021)
Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
Enabling monocular depth perception at the very edge. CVPR Workshops (2020)
Valentino Peluso, Enrico Macii, Andrea Calimera
Optimization Tools for ConvNets on the Edge. VLSI-SOC (2020)
Matteo Grimaldi, Valentino Peluso, Andrea Calimera
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. AICAS (2020)
Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou
Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231]. Integr. 70 (2020)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Luca Mocerino, Andrea Calimera
TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks. AICAS (2020)
Luca Mocerino, Andrea Calimera
TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks. CoRR (2019)
Matteo Grimaldi, Valentino Peluso, Andrea Calimera
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. CoRR (2019)
Matteo Grimaldi, Valerio Tenace, Andrea Calimera
Layer-Wise Compressive Training for Convolutional Neural Networks. Future Internet 11 (1) (2019)
Valentino Peluso, Roberto Giorgio Rizzo, Antonio Cipolletta, Andrea Calimera
Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets. SNAMS (2019)
Luca Mocerino, Andrea Calimera
CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs. ICECS (2019)
Luca Mocerino, Valerio Tenace, Andrea Calimera
Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. DATE (2019)
Matteo Grimaldi, Valentino Peluso, Andrea Calimera
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores. IEEE Access 7 (2019)
Valentino Peluso, Antonio Cipolletta, Francesco Vaiana, Andrea Calimera
Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores. ICECS (2019)
Valentino Peluso, Matteo Grimaldi, Andrea Calimera
Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. VLSI-SoC (2019)
Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. DATE (2019)
Luca Mocerino, Andrea Calimera
CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs. CoRR (2019)
Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Stefano Mattoccia
Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms. DATE (2019)
Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling. Integr. 63 (2018)
Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera
Multiplication by Inference using Classification Trees: A Case-Study Analysis. ISCAS (2018)
Marco Vacca, Yaswanth Tavva, Anupam Chattopadhyay, Andrea Calimera
Logic-In-Memory Architecture For Min/Max Search. ICECS (2018)
Valerio Tenace, Andrea Calimera
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. VLSI-SoC (2018)
Valerio Tenace, Andrea Calimera
Quasi-exact logic functions through classification trees. Integr. 63 (2018)
Matteo Grimaldi, Federico Pugliese, Valerio Tenace, Andrea Calimera
A compression-driven training framework for embedded deep neural networks. INTESA@ESWEEK (2018)
Valentino Peluso, Andrea Calimera
Energy-Driven Precision Scaling for Fixed-Point ConvNets. VLSI-SoC (2018)
Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino
All-digital embedded meters for on-line power estimation. DATE (2018)
Valentino Peluso, Andrea Calimera
Scalable-effort ConvNets for multilevel classification. ICCAD (2018)
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. DATE (2018)
Valentino Peluso, Andrea Calimera
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. VLSI-SoC (Selected Papers) (2018)
Valentino Peluso, Andrea Calimera
Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. ISCAS (2018)
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. ISCAS (2018)
Valerio Tenace, Andrea Calimera
Activation-Kernel Extraction through Machine Learning. NGCAS (2017)
Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling. VLSI-SoC (Selected Papers) (2017)
Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou, Xin Liu
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS. VLSI-SoC (2017)
Roberto Giorgio Rizzo, Andrea Calimera
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling. NGCAS (2017)
Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping. VLSI-SoC (Selected Papers) (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. VLSI-SoC (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. ISCAS (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. VLSI-SoC (Selected Papers) (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. IEEE Trans. Circuits Syst. II Express Briefs (12) (2016)
Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. VLSI-SoC (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI (2016)
Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. ACM Great Lakes Symposium on VLSI (2015)
Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino
An automated design flow for approximate circuits based on reduced precision redundancy. ICCD (2015)
Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI (2015)
Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino
Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores. ACM Great Lakes Symposium on VLSI (2015)
Felipe Lavratti, Letícia Maria Bolzani Poehls, Fabian Vargas, Andrea Calimera, Enrico Macii
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. VLSI Design (2015)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. DAC (2015)
Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems 39 (8) (2015)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. DATE (2014)
Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. 45 (5) (2014)
Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (2) (2014)
Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera, Enrico Macii, Massimo Poncino
Modeling of Physical Defects in PN Junction Based Graphene Devices. J. Electron. Test. 30 (3) (2014)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. DSD (2014)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino, Letícia Maria Veiras Bolzani Poehls
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. LATW (2013)
Sandeep Miryala, Andrea Calimera, Massimo Poncino, Enrico Macii
Exploration of different implementation styles for graphene-based reconfigurable gates. ICICDT (2013)
Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. DATE (2013)
Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Alberto Nannarelli, Massimo Poncino
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Felipe Lavratti, Letícia Maria Veiras Bolzani, Andrea Calimera, Fabian Vargas, Enrico Macii
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs. LATW (2013)
Andrea Calimera, Enrico Macii, Massimo Poncino
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. DAC (2013)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Power modeling and characterization of Graphene-based logic gates. PATMOS (2013)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
Delay model for reconfigurable logic gates based on graphene PN-junctions. ACM Great Lakes Symposium on VLSI (2013)
Alessandro Sassone, Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs. Microelectron. J. 44 (11) (2013)
Mirko Loghi, Haroon Mahmood, Andrea Calimera, Massimo Poncino, Enrico Macii
Energy-optimal caches with guaranteed lifetime. ISLPED (2012)
Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. PATMOS (2012)
Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. J. Electron. Test. 28 (3) (2012)
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
IR-drop analysis of graphene-based power distribution networks. DATE (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Andrea Calimera