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Delay model for reconfigurable logic gates based on graphene PN-junctions.
Sandeep Miryala
Andrea Calimera
Enrico Macii
Massimo Poncino
Published in:
ACM Great Lakes Symposium on VLSI (2013)
Keyphrases
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computational model
real time
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neural network
cost function
probabilistic model
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experimental data
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theoretical framework
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