Valerio Tenace

Publication Activity (10 Years)

Years Active: 2012-2021
Publications (10 Years): 20

Top Topics

Classification Trees

Logic Synthesis

Convolutional Neural Networks

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon
NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. ASAP (2021)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE (2021)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR (2020)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Matteo Grimaldi, Valerio Tenace, Andrea Calimera
Layer-Wise Compressive Training for Convolutional Neural Networks. Future Internet 11 (1) (2019)
Luca Mocerino, Valerio Tenace, Andrea Calimera
Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. DATE (2019)
Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. DATE (2019)
Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera
Multiplication by Inference using Classification Trees: A Case-Study Analysis. ISCAS (2018)
Valerio Tenace, Andrea Calimera
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. VLSI-SoC (2018)
Valerio Tenace, Andrea Calimera
Quasi-exact logic functions through classification trees. Integr. 63 (2018)
Matteo Grimaldi, Federico Pugliese, Valerio Tenace, Andrea Calimera
A compression-driven training framework for embedded deep neural networks. INTESA@ESWEEK (2018)
Valerio Tenace, Andrea Calimera
Activation-Kernel Extraction through Machine Learning. NGCAS (2017)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. VLSI-SoC (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. ISCAS (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. VLSI-SoC (Selected Papers) (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. IEEE Trans. Circuits Syst. II Express Briefs (12) (2016)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI (2016)
Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI (2015)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. DAC (2015)
Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems 39 (8) (2015)
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. DATE (2014)
Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. 45 (5) (2014)
Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI (2012)