Yukio Miyasaka

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 13

Top Topics

Parallel Algorithm

Attention Mechanism

Biologically Motivated

Top Venues

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Yukio Miyasaka
Transduction Method for AIG Minimization. ASPDAC (2024)
Jitendra Kumar, Yukio Miyasaka, Asutosh Srivastava, Masahiro Fujita
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (4) (2023)
Mingfei Yu, Yukio Miyasaka, Masahiro Fujita
Parallel Scheduling Attention Mechanism: Generalization and Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 15 (2022)
Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita
Logic Synthesis for Generalization and Learning Addition. DATE (2021)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE (2021)
Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. DATE (2020)
Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) (2020)
Yukio Miyasaka, Masahiro Fujita
SAT-Based Data-Flow Mapping Onto Array Processor. VLSI-SOC (2020)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR (2020)
Yukio Miyasaka, Akihiro Goda, Ashish Mittal, Masahiro Fujita
Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Akihiro Goda, Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. ISQED (2020)
Yukio Miyasaka, Ashish Mittal, Masahiro Fujita
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. ISQED (2019)
Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita
Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. ISCAS (2019)