John Wawrzynek

Publication Activity (10 Years)

Years Active: 1984-2024
Publications (10 Years): 40

Top Venues

CoRR

FPGA

FCCM

ICCAD

Publications

Vint Lee, Chun Deng, Leena Elzeiny, Pieter Abbeel, John Wawrzynek
Chip Placement with Diffusion. CoRR (2024)
Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE (2023)
Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek
SPADES: A Productive Design Flow for Versal Programmable Logic. FPL (2023)
Qijing Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. ISPASS (2022)
Qijing Huang, Minwoo Kang, Grace Dinh, Thomas Norell, Aravind Kalaiah, James Demmel, John Wawrzynek, Yakun Sophia Shao
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. CoRR (2021)
Qijing Huang, Aravind Kalaiah, Minwoo Kang, James Demmel, Grace Dinh, John Wawrzynek, Thomas Norell, Yakun Sophia Shao
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. ISCA (2021)
Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference. CoRR (2021)
Qijing Huang, Dequan Wang, Zhen Dong, Yizhao Gao, Yaohui Cai, Tian Li, Bichen Wu, Kurt Keutzer, John Wawrzynek
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs. FPGA (2021)
Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. FCCM (2021)
Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. CoRR (2020)
Ameer Haj-Ali, Qijing (Jenny) Huang, William S. Moses, John Xiang, Krste Asanovic, John Wawrzynek, Ion Stoica
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. MLSys (2020)
Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) (2020)
Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek
Algorithm-hardware Co-design for Deformable Convolution. CoRR (2020)
Ameer Haj-Ali, Hasan Genc, Qijing Huang, William S. Moses, John Wawrzynek, Krste Asanovic, Ion Stoica
ProTuner: Tuning Programs with Monte Carlo Tree Search. CoRR (2020)
Zhen Dong, Dequan Wang, Qijing Huang, Yizhao Gao, Yaohui Cai, Bichen Wu, Kurt Keutzer, John Wawrzynek
CoDeNet: Algorithm-hardware Co-design for Deformable Convolution. CoRR (2020)
Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanovic, John Wawrzynek
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. ICCAD (2019)
James C. Martin, Robert W. Brodersen, John Wawrzynek
Antenna Array Geometries for Directional Wireless Networks. WCNC (2019)
Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek
Algorithm-hardware Co-design for Deformable Convolution. EMC2@NeurIPS (2019)
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA (2019)
Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek
HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing. IEEE Trans. Computers 68 (8) (2019)
Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek
GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. ASP-DAC (2019)
Ameer Haj Ali, Qijing Huang, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning. CoRR (2019)
Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. FCCM (2019)
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR (2018)
James C. Martin, Robert W. Brodersen, John Wawrzynek
Receiver Adaptive Beamforming and Interference of Indoor Environments in mmWave. PIMRC (2018)
Ben Zhang, Xin Jin, Sylvia Ratnasamy, John Wawrzynek, Edward A. Lee
AWStream: adaptive wide-area streaming analytics. SIGCOMM (2018)
Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek
NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads. FCCM (2018)
Filip Lemic, Vlado Handziski, Mladen Miksa, Jan M. Rabaey, John Wawrzynek, Adam Wolisz
Selection and Aggregation of Location Information Provisioning Services. ICCCN (2017)
Shaoyi Cheng, Qijing Huang, John Wawrzynek
Synthesis of program binaries into FPGA accelerators with runtime dependence validation. FPT (2017)
Hayden Kwok-Hay So, John Wawrzynek
Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017). CoRR (2017)
Hayden Kwok-Hay So, John Wawrzynek
OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. FPGA (2017)
Simon Scott, John Wawrzynek
Compressive sensing and sparse antenna arrays for indoor 3-D microwave imaging. EUSIPCO (2017)
Filip Lemic, Vlado Handziski, Ivan Azcarate, John Wawrzynek, Jan M. Rabaey, Adam Wolisz
SLSR: A flexible middleware localization service architecture. IPIN (2017)
Hayden Kwok-Hay So, John Wawrzynek
Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016). CoRR (2016)
Shaoyi Cheng, John Wawrzynek
High Level Synthesis with a Dataflow Architectural Template. CoRR (2016)
Shaoyi Cheng, John Wawrzynek
Synthesis of statically analyzable accelerator networks from sequential programs. ICCAD (2016)
Nitesh Mor, Ben Zhang, John Kolb, Douglas S. Chan, Nikhil Goyal, Nicholas Sun, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz
Toward a Global Data Infrastructure. IEEE Internet Comput. 20 (3) (2016)
Hayden Kwok-Hay So, John Wawrzynek
OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. FPGA (2016)
Filip Lemic, Vlado Handziski, Nitesh Mor, Jan M. Rabaey, John Wawrzynek, Adam Wolisz
Toward standardized localization service. IPIN (2016)
Filip Lemic, James C. Martin, Christopher Yarp, Douglas S. Chan, Vlado Handziski, Robert W. Brodersen, Gerhard P. Fettweis, Adam Wolisz, John Wawrzynek
Localization as a feature of mmWave communication. IWCMC (2016)
Ben Zhang, Nitesh Mor, John Kolb, Douglas S. Chan, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz
The Cloud is Not Enough: Saving IoT from the Cloud. HotCloud (2015)
Mingjie Lin, Shaoyi Cheng, Ronald F. DeMara, John Wawrzynek
ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism. Microprocess. Microsystems 39 (7) (2015)
Ben Zhang, Nitesh Mor, John Kolb, Douglas S. Chan, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz
The Cloud is Not Enough: Saving IoT from the Cloud. HotStorage (2015)
Edward A. Lee, Björn Hartmann, John Kubiatowicz, Tajana Simunic Rosing, John Wawrzynek, David Wessel, Jan M. Rabaey, Kris Pister, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia, David T. Blaauw, Prabal Dutta, Kevin Fu, Carlos Guestrin, Ben Taskar, Roozbeh Jafari, Douglas L. Jones, Vijay Kumar, Rahul Mangharam, George J. Pappas, Richard M. Murray, Anthony Rowe
The Swarm at the Edge of the Cloud. IEEE Des. Test 31 (3) (2014)
Shaoyi Cheng, John Wawrzynek
Architectural synthesis of computational pipelines with decoupled memory access. FPT (2014)
Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek
Reconfigurable computing in the era of post-silicon scaling [panel discussion]. FCCM (2013)
Mingjie Lin, Shaoyi Cheng, John Wawrzynek
Extracting memory-level parallelism through reconfigurable hardware traces. ReConFig (2013)
Ilia A. Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James C. Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek
Exploring Many-Core Design Templates for FPGAs and ASICs. Int. J. Reconfigurable Comput. 2012 (2012)
Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek
Exploiting Memory-Level Parallelism in Reconfigurable Accelerators. FCCM (2012)
Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic
Chisel: constructing hardware in a Scala embedded language. DAC (2012)
Mingjie Lin, Yu Bai, John Wawrzynek
Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience. J. Electr. Comput. Eng. 2012 (2012)
Mingjie Lin, Yu Bai, John Wawrzynek
Discriminatively Fortified Computing with Reconfigurable Digital Fabric. HASE (2011)
John Wawrzynek
Should the academic community launch an open-source FPGA device and tools effort?: evening panel. FPGA (2011)
John Lazzaro, John Wawrzynek
RTP Payload Format for MIDI. RFC 6295 (2011)
John Wawrzynek
Advances and challenges of computing with FPGAs. CICC (2011)
Mingjie Lin, Shaoyi Cheng, John Wawrzynek
Using many-core architectural templates for FPGA-based computing (abstract only). FPGA (2011)
Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek
Bridging the GPGPU-FPGA efficiency gap. FPGA (2011)
Mingjie Lin, Ilia A. Lebedev, John Wawrzynek
High-throughput bayesian computing machine with reconfigurable hardware. FPGA (2010)
Mingjie Lin, John Wawrzynek, Abbas El Gamal
Exploring FPGA Routing Architecture Stochastically. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (10) (2010)
Ilia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James C. Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek
MARC: A Many-Core Approach to Reconfigurable Computing. ReConFig (2010)
Mingjie Lin, Shaoyi Cheng, John Wawrzynek
Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations. ReConFig (2010)
Mingjie Lin, John Wawrzynek
Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (12) (2010)
Mingjie Lin, Ilia A. Lebedev, John Wawrzynek
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices. FPL (2010)
Narges Bani Asadi, Christopher W. Fletcher, Greg Gibeling, John Wawrzynek, Wing H. Wong, Garry P. Nolan
: a massively parallel, scalable system for learning interaction networks on FPGAs. ICS (2010)
Krste Asanovic, Rastislav Bodík, James Demmel, Tony M. Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, Katherine A. Yelick
A view of the parallel computing landscape. Commun. ACM 52 (10) (2009)
Yury Markovsky, Yatish Patel, John Wawrzynek
Using adaptive routing to compensate for performance heterogeneity. NOCS (2009)
Marghoob Mohiyuddin, Mark Murphy, Leonid Oliker, John Shalf, John Wawrzynek, Samuel Williams
A design methodology for domain-optimized power-efficient supercomputing. SC (2009)
Jan M. Rabaey, Daniel Burke, Ken Lutz, John Wawrzynek
Workloads of the Future. IEEE Des. Test Comput. 25 (4) (2008)
John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27 (2) (2007)
Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz
RAMP Blue: A Message-Passing Manycore System in FPGAs. FPL (2007)
John Wawrzynek
Adventures with a Reconfigurable Research Platform. FPL (2007)
John Lazzaro, John Wawrzynek
RTP Payload Format for MIDI. RFC 4695 (2006)
André DeHon, Randy Huang, John Wawrzynek
Stochastic spatial routing for reconfigurable networks. Microprocess. Microsystems 30 (6) (2006)
John Lazzaro, John Wawrzynek
An Implementation Guide for RTP MIDI. RFC 4696 (2006)
David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek
Research accelerator for multiple processors. Hot Chips Symposium (2006)
André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
Stream computations organized for reconfigurable execution. Microprocess. Microsystems 30 (6) (2006)
Zohair Hyder, John Wawrzynek
Defect Tolerance in Multiple-FPGA Systems. FPL (2005)
Chen Chang, John Wawrzynek, Robert W. Brodersen
BEE2: A High-End Reconfigurable Computing System. IEEE Des. Test Comput. 22 (2) (2005)
Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen
The Design And Application Of A High-End Reconfigurable Computing System. ERSA (2005)
Nicholas Weaver, John R. Hauser, John Wawrzynek
The SFRA: a corner-turn FPGA architecture. FPGA (2004)
Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek
Post-placement C-slow retiming for the xilinx virtex FPGA. FPGA (2003)
Randy Huang, John Wawrzynek, André DeHon
Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA (2003)
Joseph Yeh, John Wawrzynek
Quality based compute-resource allocation in real-time signal processing. ICASSP (2) (2003)
John Wawrzynek, Keith Diefendorff
Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics. IEEE Micro 23 (2) (2003)
Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA (2002)
André DeHon, Randy Huang, John Wawrzynek
Hardware-Assisted Fast Routing. FCCM (2002)
Nicholas Weaver, John Wawrzynek
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. FCCM (2002)
John Lazzaro, John Wawrzynek
A case for network musical performance. NOSSDAV (2001)
Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon
Stream Computations Organized for Reconfigurable Execution (SCORE). FPL (2000)
Nicholas Weaver, John Wawrzynek
A Comparison of the AES Candidates Amenability to FPGA Implementation. AES Candidate Conference (2000)
Timothy J. Callahan, John Wawrzynek
Adapting software pipelining for reconfigurable computing. CASES (2000)
Timothy J. Callahan, John R. Hauser, John Wawrzynek
The Garp Architecture and C Compiler. Computer 33 (4) (2000)
John Lazzaro, John Wawrzynek
JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure. Neural Comput. 11 (1) (1999)
William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA (1999)
Norman P. Jouppi, John Wawrzynek
Real products, real technology Guest Editor's Introduction]. IEEE Micro 19 (2) (1999)
André DeHon, John Wawrzynek
Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC (1999)
Todd D. Hodes, John R. Hauser, John Wawrzynek, Adrian Freed, David Wessel
A fixed-point recursive digital oscillator for additive synthesis of audio. ICASSP (1999)
Timothy J. Callahan, John Wawrzynek
Instruction-Level Parallelism for Reconfigurable Computing. FPL (1998)
Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek
Object Oriented Circuit-Generators in Java. FCCM (1998)
Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek
Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA (1998)

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Publication Activity (10 Years)

Top Topics

Top Venues

John Wawrzynek