Andrew Waterman

Publication Activity (10 Years)

Years Active: 2009-2020
Publications (10 Years): 4

Top Topics

Instruction Set

Ibm Power Processor

Computation Intensive

Top Venues

Hot Chips Symposium

Publications

Yunsup Lee, Andrew Waterman
Managing Chip Design Complexity in the Domain-Specific SoC Era. VLSI Circuits (2020)
David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. FPGA (2019)
Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51 (4) (2016)
Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic
An Agile Approach to Building RISC-V Microprocessors. IEEE Micro 36 (2) (2016)
Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC (2015)
Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium (2015)
Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael Georgas, Andrew Waterman, Jeffrey M. Shainline, Rimas Avizienis, Sen Lin, Benjamin Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry Cook, Albert J. Ou, Jonathan Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic
Single-chip microprocessor that communicates directly using light. Nat. 528 (7581) (2015)
Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. ESSCIRC (2014)
Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David A. Patterson, Krste Asanovic
The RISC-V instruction set. Hot Chips Symposium (2013)
Yunsup Lee, David Sheffield, Andrew Waterman, Michael J. Anderson, Kurt Keutzer, Krste Asanovic
Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition. Hot Chips Symposium (2013)
Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic
Chisel: constructing hardware in a Scala embedded language. DAC (2012)
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson
A case for FAME: FPGA architecture model execution. ISCA (2010)
Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic
RAMP gold: an FPGA-based architecture simulator for multiprocessors. DAC (2010)
Samuel Williams, Andrew Waterman, David A. Patterson
Roofline: an insightful visual performance model for multicore architectures. Commun. ACM 52 (4) (2009)