Giulio Gambardella

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 28

Top Topics

Fault Tolerance

Hardware Architectures

Variable Precision

Eigenvalues And Eigenvectors

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Timoteo García Bertoa, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, John McAllister
Fault-Tolerant Neural Network Accelerators With Selective TMR. IEEE Des. Test 40 (2) (2023)
Syed Asad Alam, David Gregg, Giulio Gambardella, Thomas B. Preußer, Michaela Blott
On the RTL Implementation of FINN Matrix Vector Unit. ACM Trans. Embed. Comput. Syst. 22 (6) (2023)
Syed Asad Alam, David Gregg, Giulio Gambardella, Michael Preußer, Michaela Blott
On the RTL Implementation of FINN Matrix Vector Compute Unit. CoRR (2022)
Michaela Blott, Nicholas J. Fraser, Giulio Gambardella, Lisa Halder, Johannes Kath, Zachary Neveu, Yaman Umuroglu, Alina Vasilciuc, Miriam Leeser, Linda Doyle
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach. IEEE Trans. Computers 70 (10) (2021)
Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. CoRR (2020)
Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. FPGA (2020)
Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. ITC (2020)
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT (2019)
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA (2019)
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR (2019)
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR (2018)
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC (2018)
Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. CoRR (2018)
Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott
Inference of quantized neural networks on heterogeneous all-programmable devices. DATE (2018)
Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott
FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs. CoRR (2018)
Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs. FPL (2018)
Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott
Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices. CoRR (2018)
Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. CoRR (2018)
Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers
: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 11 (3) (2018)
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR (2018)
Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland
Customizing Low-Precision Deep Neural Networks for FPGAs. FPL (2018)
Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
Scaling Binarized Neural Networks on Reconfigurable Logic. CoRR (2017)
Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. ICONIP (2) (2017)
Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
Scaling Binarized Neural Networks on Reconfigurable Logic. PARMA-DITAM@HiPEAC (2017)
Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. FPGA (2017)
Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. CoRR (2017)
Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. ICCD (2017)
Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. CoRR (2016)
Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs. ACM Trans. Reconfigurable Technol. Syst. 8 (1) (2015)
Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Frank Reichenbach, Trond Løkstad, Gulzaib Rafiq
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems. DSD (2014)
Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Alessandro Vallero
A novel methodology to increase fault tolerance in autonomous FPGA-based systems. IOLTS (2014)
Teodora Sanislav, George Dan Mois, Silviu Folea, Liviu Miclea, Giulio Gambardella, Paolo Prinetto
A cloud-based Cyber-Physical System for environmental monitoring. MECO (2014)
Stefano Di Carlo, Giulio Gambardella, Trong Huynh Bao, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
ZipStream: Improving dependability in dynamic partial reconfiguration. IDT (2013)
Stefano Di Carlo, Giulio Gambardella, Piergiorgio Lanza, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications. IDT (2013)
Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Piergiorgio Lanza
FEMIP: A high performance FPGA-based features extractor & matcher for space applications. FPL (2013)
Stefano Di Carlo, Giulio Gambardella, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
Fault mitigation strategies for CUDA GPUs. ITC (2013)
Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
Increasing the robustness of CUDA Fermi GPU-based systems. IOLTS (2013)
Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
A software-based self test of CUDA Fermi GPUs. ETS (2013)
Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS. FPL (2013)
Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto
Validation & Verification of an EDA automated synthesis tool. IDT (2011)
Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Gabriele Tiotto, Paolo Prinetto
An area-efficient 2-D convolution implementation on FPGA for space applications. IDT (2011)
Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto
A unifying formalism to support automated synthesis of SBSTs for embedded caches. EWDTS (2011)
Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches. Asian Test Symposium (2011)