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An area-efficient 2-D convolution implementation on FPGA for space applications.
Stefano Di Carlo
Giulio Gambardella
Marco Indaco
Daniele Rolfo
Gabriele Tiotto
Paolo Prinetto
Published in:
IDT (2011)
Keyphrases
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efficient implementation
hardware implementation
search space
computationally expensive
highly optimized
hardware architectures
real time
information systems
image processing
computationally efficient
computing systems
higher dimensional
parallel architecture
hardware architecture
low overhead
digital signal