Peter Y. K. Cheung

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 37

Top Venues

CoRR

FCCM

FPL

ACM Trans. Reconfigurable Technol. Syst.

Publications

Le Yu, Zhiheng Liang, Yaqi Li, Shiwei Zhang, Yiren Zhao, Peter Y. K. Cheung
Verification and Fault Injection Platform Based on MTB Stimulus Generation Method for L2 Deep Market Quote Decoder. IEEE Access 12 (2024)
Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. 22 (6) (2023)
Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed Abdelfattah
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA (2022)
Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys (2021)
Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
Enabling Binary Neural Network Training on the Edge. CoRR (2021)
Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed Abdelfattah
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR (2021)
Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. ASAP (2021)
Michelangelo Bin, Peter Y. K. Cheung, Emanuele Crisostomi, Pietro Ferraro, Hugo Lhachemi, Roderick Murray-Smith, Connor Myant, Thomas Parisini, Robert Shorten, Sebastian Stein, Lewi Stone
Post-lockdown abatement of COVID-19 by fast periodic switching. PLoS Comput. Biol. 17 (1) (2021)
Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. CoRR (2021)
Michelangelo Bin, Peter Y. K. Cheung, Emanuele Crisostomi, Pietro Ferraro, Connor Myant, Thomas Parisini, Robert Shorten
On Fast Multi-Shot Epidemic Interventions for Post Lock-Down Mitigation: Implications for Simple Covid-19 Models. CoRR (2020)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers 69 (12) (2020)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR (2019)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM (2019)
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR (2019)
Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL (2019)
Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung
Context-based image acquisition from memory in digital systems. J. Real Time Image Process. 16 (4) (2019)
Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR (2019)
Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT (2019)
Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52 (2) (2019)
Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR (2019)
Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT (2018)
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC (2018)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok
CypherDB: A Novel Architecture for Outsourcing Secure Database Processing. IEEE Trans. Cloud Comput. 6 (2) (2018)
Erwei Wang, James J. Davis, Peter Y. K. Cheung
A PYNQ-Based Framework for Rapid CNN Prototyping. FCCM (2018)
Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
Hardware Compilation of Deep Neural Networks: An Overview. ASAP (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL (2018)
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR (2018)
Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. ARC (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
STRIPE: Signal selection for runtime power estimation. FPL (2017)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34 (6) (2017)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA (2016)
Jiang Su, David B. Thomas, Peter Y. K. Cheung
Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. FCCM (2016)
James J. Davis, Peter Y. K. Cheung
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. ARC (2016)
Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM (2016)
Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News 44 (4) (2016)
Andrew Bean, Nachiket Kapre, Peter Y. K. Cheung
G-DMA: improving memory access performance for hardware accelerated sparse graph computation. ReConFig (2015)
Peter Y. K. Cheung, Wayne Luk, Cristina Silvano
Preface. FPL (2015)
Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 7 (4) (2015)
Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok
An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine. FPT (2015)
James J. Davis, Peter Y. K. Cheung
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. FPL (2014)
Jianxiong Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung
Image progressive acquisition for hardware systems. DATE (2014)
Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung
Dynamic voltage & frequency scaling with online slack measurement. FPGA (2014)
Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung
Kernel-based Adaptive Image Sampling. VISAPP (1) (2014)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express 11 (3) (2014)
James J. Davis, Peter Y. K. Cheung
Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. FCCM (2014)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express 11 (3) (2014)
Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre
Timing Fault Detection in FPGA-Based Circuits. FCCM (2014)
Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk
SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM (2014)
James J. Davis, Peter Y. K. Cheung
Datapath fault tolerance for parallel accelerators. FPT (2013)
Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC (2013)
Justin S. J. Wong, Peter Y. K. Cheung
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung
Domain-specific progressive sampling of face images. GlobalSIP (2013)
Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski
Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News 41 (5) (2013)
Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung
Variation and Reliability in FPGAs. IEEE Des. Test 30 (6) (2013)
Thomas C. P. Chau, Ka-Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk
Acceleration of real-time Proximity Query for dynamic active constraints. FPT (2013)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL (2013)
Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration. J. Syst. Archit. 59 (10-D) (2013)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
A variation-adaptive retiming method exploiting reconfigurability. FPL (2013)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT (2013)
Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski
Adaptive Sequential Monte Carlo approach for real-time applications. FPL (2012)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL (2012)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM (2012)
Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
Early performance estimation of image compression methods on soft processors. FPL (2012)
Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung
Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Comput. Archit. News 40 (5) (2012)
Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung
Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. IET Comput. Digit. Tech. 5 (4) (2011)
Justin S. J. Wong, Peter Y. K. Cheung
Improved delay measurement method in FPGA based on transition probability. FPGA (2011)
Peter Y. K. Cheung
Introduction to special section FPGA 2009. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. 58 (8) (2011)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA (2011)
Sumanta Chaudhuri, Justin S. J. Wong, Peter Y. K. Cheung
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT (2011)
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. 54 (1) (2011)
Edward A. Stott, Peter Y. K. Cheung
Improving FPGA Reliability with Wear-Levelling. FPL (2011)
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
GPU Versus FPGA for High Productivity Computing. FPL (2010)
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (8) (2010)
Yan Wu, P. Kuvinichkul, Peter Y. K. Cheung, Yiannis Demiris
Towards anthropomorphic robot Thereminist. ROBIO (2010)
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa
Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfigurable Comput. 2010 (2010)
Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung
Exploration of hardware sharing for image encoders. DATE (2010)
Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. IEEE Trans. Very Large Scale Integr. Syst. 18 (3) (2010)
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers 59 (4) (2010)
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech. 4 (3) (2010)
David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
A Salient Region Detector for GPU Using a Cellular Automata Architecture. ICONIP (2) (2010)
Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)
Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15 (2) (2010)
Tobias Becker, Wayne Luk, Peter Y. K. Cheung
Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM (2010)
Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung
Degradation Analysis and Mitigation in FPGAs. FPL (2010)
Peter Y. K. Cheung
Process Variability and Degradation: New Frontier for Reconfigurable. ARC (2010)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. 43 (2) (2010)
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. 3 (3) (2010)
Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
Degradation in FPGAs: measurement and modelling. FPGA (2010)
Tobias Becker, Wayne Luk, Peter Y. K. Cheung
Parametric Design for Reconfigurable Software-Defined Radio. ARC (2009)
Philip G. Potter, Wayne Luk, Peter Y. K. Cheung
Partition-based exploration for reconfigurable JPEG designs. DATE (2009)
Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. 14 (3) (2009)
Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT (2009)
Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung
A sensor-based approach to linear blur identification for real-time video enhancement. ICIP (2009)
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
Area estimation and optimisation of FPGA routing fabrics. FPL (2009)
Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen
Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM (2009)
Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1 (4) (2009)

Peter Y. K. Cheung.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Peter Y. K. Cheung