Joshua M. Levine

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 12

Top Topics

Field Programmable Gate Array

Fault Detection

Top Venues

Publications

Ce Guo, Wayne Luk, Alexander Warren, Joshua M. Levine, Peter Brookes
Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test. ASAP (2023)
Ce Guo, Diego Cupello, Wayne Luk, Joshua M. Levine, Alexander Warren, Peter Brookes
FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization. FPL (2023)
Ce Guo, Wayne Luk, Stanley Qing Shui Loh, Alexander Warren, Joshua M. Levine
Customisable Control Policy Learning for Robotics. ASAP (2019)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL (2018)
Fei Xia, Ashur Rafiev, Ali Aalsaud, Mohammed A. Noaman Al-Hayanni, James J. Davis, Joshua M. Levine, Andrey Mokhov, Alexander B. Romanovsky, Rishad A. Shafik, Alex Yakovlev, Sheng Yang
Voltage, Throughput, Power, Reliability, and Multicore Scaling. Computer 50 (8) (2017)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
STRIPE: Signal selection for runtime power estimation. FPL (2017)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34 (6) (2017)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA (2016)
Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM (2016)
Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk
Delay-Bounded Routing for Shadow Registers. FPGA (2015)
Sheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis, Bashir M. Al-Hashimi
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. PATMOS (2015)
Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung
Dynamic voltage & frequency scaling with online slack measurement. FPGA (2014)
Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre
Timing Fault Detection in FPGA-Based Circuits. FCCM (2014)
Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung
Variation and Reliability in FPGAs. IEEE Des. Test 30 (6) (2013)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL (2013)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM (2012)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA (2011)