Eddie Hung

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 16

Top Topics

Parallel Implementation

Fpga Technology

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Chris Lavin, Eddie Hung
Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. ICCAD (2023)
Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE (2023)
Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Hossein Omidian, Eddie Hung, Dinesh Gaitonde
100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. ARC (2022)
David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. FCCM (2019)
David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic
Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. CoRR (2019)
Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung
EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. FCCM (2019)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL (2018)
Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. ETS (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
STRIPE: Signal selection for runtime power estimation. FPL (2017)
Eddie Hung, Tim Todman, Wayne Luk
Transparent In-Circuit Assertions for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34 (6) (2017)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA (2016)
Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. CoRR (2016)
Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM (2016)
Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk
Delay-Bounded Routing for Shadow Registers. FPGA (2015)
Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk
Accelerating SpMV on FPGAs by Compressing Nonzero Values. FCCM (2015)
Eddie Hung
Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry. FPL (2015)
Eddie Hung, Steven J. E. Wilton
Incremental Trace-Buffer Insertion for FPGA Debug. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Eddie Hung, Steven J. E. Wilton
Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Design Autom. Electr. Syst. 19 (2) (2014)
Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton
Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. ARC (2014)
Eddie Hung, Tim Todman, Wayne Luk
Transparent insertion of latency-oblivious logic onto FPGAs. FPL (2014)
Eddie Hung, Steven J. E. Wilton
Scalable Signal Selection for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton
Maximum flow algorithms for maximum observability during FPGA debug. FPT (2013)
Eddie Hung, Steven J. E. Wilton
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. FPGA (2013)
Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. FCCM (2013)
Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton
Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. IEEE Des. Test 30 (4) (2013)
Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung
Rapid RTL-based signal ranking for FPGA prototyping. FPT (2012)
Eddie Hung, Steven J. E. Wilton
Limitations of incremental signal-tracing for FPGA debug. FPL (2012)
José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012)
Eddie Hung, Steven J. E. Wilton
On evaluating signal selection algorithms for post-silicon debug. ISQED (2011)
Eddie Hung, Steven J. E. Wilton
Speculative Debug Insertion for FPGAs. FPL (2011)
Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong
A detailed delay path model for FPGAs. FPT (2009)
José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras
A configurable and programmable motion estimation processor for the H.264 video codec. FPL (2008)