José Luis Núñez-Yáñez

ORCID

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 13

Top Venues

FPL

IEEE Trans. Computers

NORCAS

ACM Trans. Embed. Comput. Syst.

Loughborough University, UK (PHD)

Education History

Loughborough University, UK

PHD

Publications

Minxuan Kong, José Luis Núñez-Yáñez
Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network. ARC (2022)
Minxuan Kong, Kris Nikov, José Luis Núñez-Yáñez
Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks. DSD (2022)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (6) (2020)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Dynamic Energy Management of FPGA Accelerators in Embedded Systems. ACM Trans. Embed. Comput. Syst. 17 (3) (2018)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. FPL (2017)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Pipelined Streaming Computation of Histogram in FPGA OpenCL. PARCO (2017)
Mohd Amiruddin Zainol, José Luis Núñez-Yáñez
CPCIe: A compression-enabled PCIe core for energy and performance optimization. NORCAS (2016)
José Luis Núñez-Yáñez, Mohammad Hosseinabady, Arash Beldachi
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. IEEE Trans. Computers 65 (5) (2016)
Awais Hussain Sani, José Luis Núñez-Yáñez
Energy proportional computing with OpenCL on a FPGA-based overlay architecture. NORCAS (2016)
Juan Carlos Moctezuma, Joseph P. McGeehan, José Luis Núñez-Yáñez
Biologically compatible neural networks with reconfigurable hardware. Microprocess. Microsystems 39 (8) (2015)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. FPL (2015)
José Luis Núñez-Yáñez
Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs. IEEE Trans. Computers 64 (1) (2015)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Energy optimization of FPGA-based stream-oriented computing with power gating. FPL (2015)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Run-time power gating in hybrid ARM-FPGA devices. FPL (2014)
Juan Carlos Moctezuma, José Luis Núñez-Yáñez, Joseph P. McGeehan
Neuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation. IJCCI (NCTA) (2014)
Jin Chen, José Luis Núñez-Yáñez, Alin Achim
Bayesian Video Super-Resolution With Heavy-Tailed Prior Models. IEEE Trans. Circuits Syst. Video Technol. 24 (6) (2014)
Juan Carlos Moctezuma, Joseph McGeehan, José Luis Núñez-Yáñez
Numerically efficient and biophysically accurate neuroprocessing platform. ReConFig (2013)
Yiwei Zhang, Joseph McGeehan, Edward Regan, Stephen Kelly, José Luis Núñez-Yáñez
Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic. IEEE Trans. Computers 62 (3) (2013)
Atukem Nabina, José Luis Núñez-Yáñez
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform. ACM Trans. Reconfigurable Technol. Syst. 5 (4) (2012)
Xiaolin Chen, Nishan Canagarajah, José Luis Núñez-Yáñez, Raffaele Vitulli
Lossless video compression based on backward adaptive pixel-based fast motion estimation. Signal Process. Image Commun. 27 (9) (2012)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. IET Comput. Digit. Tech. 6 (6) (2012)
José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012)
Mohammad Hosseinabady, José Luis Núñez-Yáñez
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. IET Comput. Digit. Tech. 6 (1) (2012)
Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola
Task Dispersal Measurement in Dynamic Reconfigurable NoCs. ISVLSI (2010)
Wei Song, Doug A. Edwards, José Luis Núñez-Yáñez, Sohini Dasgupta
Adaptive stochastic routing in fault-tolerant on-chip networks. NOCS (2009)
Trevor Spiteri, George Vafiadis, José Luis Núñez-Yáñez
A toolset for the analysis and optimization of motion estimation algorithms and processors. FPL (2009)
José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras
A configurable and programmable motion estimation processor for the H.264 video codec. FPL (2008)
José Luis Núñez-Yáñez, Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli
Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture. AHS (2008)
Xiaolin Chen, Nishan Canagarajah, José Luis Núñez-Yáñez, Raffaele Vitulli
Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding. SoCC (2007)

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Publication Activity (10 Years)

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José Luis Núñez-Yáñez