Doug A. Edwards

Publication Activity (10 Years)

Years Active: 2000-2015
Publications (10 Years): 0

Top Topics

Logic Synthesis

Statistical Analyses

Top Venues

Publications

Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards
De-elastisation: from asynchronous dataflows to synchronous circuits. DATE (2015)
Wei Song, Jim D. Garside, Doug A. Edwards
Automatic data path extraction in large-scale register-transfer level designs. ISCAS (2014)
Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. DSD (2014)
Zheng Xie, Doug A. Edwards
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits. VLSI Design 2013 (2013)
Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge
Area efficient asynchronous SDM routers using 2-stage Clos switches. DATE (2012)
Wei Song, Doug A. Edwards
Asynchronous spatial division multiplexing router. Microprocess. Microsystems 35 (2) (2011)
Wei Song, Doug A. Edwards
A low latency wormhole router for asynchronous on-chip networks. ASP-DAC (2010)
Wei Song, Doug A. Edwards
An Asynchronous Routing Algorithm for Clos Networks. ACSD (2010)
Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana
Description-Level Optimisation of Synthesisable Asynchronous Circuits. DSD (2010)
Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A. Tarazona
Asynchronous Data-Driven Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 18 (7) (2010)
Zheng Xie, Doug A. Edwards
Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits. DDECS (2010)
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. DSD (2009)
P. Balasubramanian, Doug A. Edwards
Dual-Sum Single-Carry Self-Timed Adder Designs. ISVLSI (2009)
Wei Song, Doug A. Edwards, José Luis Núñez-Yáñez, Sohini Dasgupta
Adaptive stochastic routing in fault-tolerant on-chip networks. NOCS (2009)
William B. Toms, Doug A. Edwards
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks. ASYNC (2009)
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
Teak: A Token-Flow Implementation for the Balsa Language. ACSD (2009)
José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Digit. Tech. 2 (3) (2008)
Sam Taylor, Doug A. Edwards, Luis A. Plana
Automatic Compilation of Data-Driven Circuits. ASYNC (2008)
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley
Performance-driven syntax-directed synthesis of asynchronous processors. CASES (2007)
Luis A. Plana, Sam Taylor, Doug A. Edwards
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. ICCD (2005)
Nitin Gupta, Doug A. Edwards
Synthesis of Asynchronous Circuits Using Early Data Validity. VLSI Design (2005)
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards
A Burst-Mode Oriented Back-End for the Balsa Synthesis System. DATE (2002)
Doug A. Edwards, Andrew Bardsley
Balsa: An Asynchronous Hardware Synthesis Language. Comput. J. 45 (1) (2002)
Andrew Bardsley, Doug A. Edwards
Synthesising an asynchronous DMA controller with Balsa. J. Syst. Archit. 46 (14) (2000)