Jim D. Garside

Publication Activity (10 Years)

Years Active: 1992-2021
Publications (10 Years): 21

Top Topics

Bellman Residual

Top Venues

Publications

Sebastian Höppner, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Marco Stolba, Florian Kelber, Bernhard Vogginger, Felix Neumärker, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Thomas Hocker, Dennis Walter, Gengting Liu, Jim D. Garside, Steve B. Furber, Christian Mayr
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. CoRR (2021)
Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks. Simul. Model. Pract. Theory 103 (2020)
Luis A. Plana, Jim D. Garside, Jonathan Heathcote, Jeffrey Pepper, Steve Temple, Simon Davidson, Mikel Luján, Steve B. Furber
spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System. IEEE Access 8 (2020)
Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumaerker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr
Dynamic Power Management for Neuromorphic Many-Core Systems. CoRR (2019)
Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr
Dynamic Power Management for Neuromorphic Many-Core Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Mantas Mikaitis, David R. Lester, Delong Shang, Steve B. Furber, Gengting Liu, Jim D. Garside, Stefan Scholze, Sebastian Höppner, Andreas Dixius
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. ARITH (2018)
Robert James, Jim D. Garside, Luis A. Plana, Andrew Rowley, Steve B. Furber
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application. IEEE Trans. Biomed. Circuits Syst. 12 (5) (2018)
Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS (2017)
Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, John Goodacre, Mikel Luján
HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation. VEE (2017)
Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Prateek Joshi, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS (2017)
Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Luján
Low overhead dynamic binary translation on ARM. PLDI (2017)
Robert James, Jim D. Garside, Michael Hopkins, Luis A. Plana, Steve Temple, Simon Davidson, Steve B. Furber
Parallel distribution of an inner hair cell and auditory nerve model for real-time application. BioCAS (2017)
Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. FPL (2017)
Mahdi Jelodari Mamaghani, Milos Krstic, Jim D. Garside
Automatic Clock: A Promising Approach toward GALSification. ASYNC (2016)
Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Luján
Optimizing Indirect Branches in Dynamic Binary Translators. ACM Trans. Archit. Code Optim. 13 (1) (2016)
Mahdi Jelodari Mamaghani, Danil Sokolov, Jim D. Garside
Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis. ACSD (2016)
Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
HAPPY: Hybrid Address-based Page Policy in DRAMs. MEMSYS (2016)
Wei Song, Dirk Koch, Mikel Luján, Jim D. Garside
Parallel Hardware Merge Sorter. FCCM (2016)
Andrew Mundy, Jonathan Heathcote, Jim D. Garside
On-chip order-exploiting routing table minimization for a multicast supercomputer network. HPSR (2016)
Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. MEMSYS (2016)
Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards
De-elastisation: from asynchronous dataflows to synchronous circuits. DATE (2015)
Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. FCCM (2015)
Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
HAPPY: Hybrid Address-based Page Policy in DRAMs. CoRR (2015)
Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, Mikel Luján
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. CoRR (2015)
Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján
Analysis of FPGA and software approaches to simulate unconventional computer architectures. ReConFig (2015)
Guangda Zhang, Jim D. Garside, Wei Song, Javier Navaridas, Zhiying Wang
Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults. ASYNC (2015)
Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, Jim D. Garside, Kier J. Dugan, Luis A. Plana, Steve Temple
SpiNNaker - Programming Model. IEEE Trans. Computers 64 (6) (2015)
Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults. ASYNC (2014)
Wei Song, Jim D. Garside, Doug A. Edwards
Automatic data path extraction in large-scale register-transfer level designs. ISCAS (2014)
Wei Song, Guangda Zhang, Jim D. Garside
On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. ACM Great Lakes Symposium on VLSI (2014)
Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. DSD (2014)
Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. Microprocess. Microsystems 38 (8) (2014)
Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown
Overview of the SpiNNaker System Architecture. IEEE Trans. Computers 62 (12) (2013)
Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
Transient Fault Tolerant QDI Interconnects Using Redundant Check Code. DSD (2013)
Wei Song, Jim D. Garside
Automatic Controller Detection for Large Scale RTL Designs. DSD (2013)
Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. Parallel Comput. 39 (11) (2013)
Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. IEEE J. Solid State Circuits 48 (8) (2013)
Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. ASYNC (2012)
Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge
Area efficient asynchronous SDM routers using 2-stage Clos switches. DATE (2012)
Geoffrey Ndu, Jim D. Garside
Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration. ARC (2012)
Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve B. Furber
Scalable communications for a million-core neural processing architecture. J. Parallel Distributed Comput. 72 (11) (2012)
Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC (2012)
Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. 7 (4) (2011)
Jian Wu, Steve B. Furber, Jim D. Garside
A Programmable Adaptive Router for a GALS Parallel System. ASYNC (2009)
Jim D. Garside, Stephen B. Furber, Steve Temple, Viv Woods
The Amulet chips: Architectural development for asynchronous microprocessors. ICECS (2009)
Yebin Shi, Steve B. Furber, Jim D. Garside, Luis A. Plana
Fault Tolerant Delay Insensitive Inter-chip Communication. ASYNC (2009)
Konstantinos Nikas, Matthew Horsnell, Jim D. Garside
An adaptive bloom filter cache partitioning scheme for multicore architectures. ICSAMOS (2008)
A. Robinson, Jim D. Garside
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. ACM Great Lakes Symposium on VLSI (2007)
Saeid Nooshabadi, Jim D. Garside
Modernization of teaching in embedded systems design - an international collaborative project. IEEE Trans. Educ. 49 (2) (2006)
Charlie Brej, Jim D. Garside
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design (2005)
Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou
A Low-Power Processor Architecture Optimized forWireless Devices. ASAP (2005)
Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC (2004)
Aristides Efthymiou, Jim D. Garside
A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. Very Large Scale Integr. Syst. 12 (3) (2004)
Aristides Efthymiou, Jim D. Garside
Adaptive Pipeline Structures fo Speculation Control. ASYNC (2003)
Luis A. Plana, Peter A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu
SPA - a secure Amulet core for smartcard applications. Microprocess. Microsystems 27 (9) (2003)
Daranee Hormdee, Jim D. Garside, Stephen B. Furber
An asynchronous copy-back cache architecture. Microprocess. Microsystems 27 (10) (2003)
Daranee Hormdee, Jim D. Garside, Stephen B. Furber
An Asynchronous Victim Cache. DSD (2002)
Aristides Efthymiou, Jim D. Garside
An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED (2002)
W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Peter A. Riocreux, Luis A. Plana
SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC (2002)
Aristides Efthymiou, Jim D. Garside
Adaptive Pipeline Depth Control for Processor Power-Management. ICCD (2002)
Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
Logic Design of Asynchronous Circuits (Tutorial Abstract). VLSI Design (2002)
Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
Power Management in the Amulet Microprocessors. IEEE Des. Test Comput. 18 (2) (2001)
Daranee Hormdee, Jim D. Garside
AMULET3i Cache Architecture. ASYNC (2001)
David W. Lloyd, Jim D. Garside
A Practical Comparison of Asynchronous Design Styles. ASYNC (2001)
Stephen B. Furber, David A. Edwards, Jim D. Garside
AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD (2000)
Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, Siamak Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli
AMULET3i - An Asynchronous System-on-Chip. ASYNC (2000)
David W. Lloyd, Jim D. Garside, D. A. Gilbert
Memory Faults in Asynchronous Microprocessors. ASYNC (1999)
Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ASYNC (1999)
Jim D. Garside, Stephen B. Furber, S.-H. Chung
AMULET3 Revealed. ASYNC (1999)
Stephen B. Furber, Jim D. Garside, D. A. Gilbert
AMULET3: a high-performance self-timed ARM microprocessor. ICCD (1998)
Stephen B. Furber, Jim D. Garside, Steve Temple, Paul Day, Nigel C. Paver
Asynchronous Embedded Control. Integr. Comput. Aided Eng. 5 (1) (1998)
Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver
AMULET2e: An Asynchronous Embedded Controller. ASYNC (1997)
John V. Woods, Paul Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple
AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers 46 (4) (1997)
D. A. Gilbert, Jim D. Garside
A Result Forwarding Mechanism for Asynchronous Pipelined Systems. ASYNC (1997)
Jim D. Garside, Steve Temple, Rahul Mehra
The AMULET2e cache system. ASYNC (1996)
Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods
The Design and Evaluation of an Asynchronous Microprocessor. ICCD (1994)
Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods
AMULET1: A Micropipelined ARM. COMPCON (1994)
Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods
A micropipelined ARM. VLSI (1993)
Jim D. Garside
A CMOS VLSI Implementation of an Asynchronous ALU. Asynchronous Design Methodologies (1993)
N. C. Paver, Paul Day, Stephen B. Furber, Jim D. Garside, John V. Woods
Register Locking in an Asynchronous Microprocessor. ICCD (1992)