Dennis Walter

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 16

Top Venues

CoRR

DAC

DATE

MIXDES

University of Bremen (PHD)

Education History

University of Bremen

PHD

Publications

Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. CoRR (2023)
Hector A. Gonzalez, Bernhard Vogginger, Chen Liu, Marco Stolba, Florian Kelber, Heiner Bauer, Stefan Hänzsche, Stefan Scholze, Marc Berthel, Tim Rosmeisl, Liyuan Guo, Dennis Walter, Piash Das, Khaleelulla Khan Nazeer, Tilo Schubert, Sebastian Höppner, Christian Mayr
A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power. CICC (2023)
Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. ISOCC (2023)
Matthias Jobst, Johannes Partzsch, Chen Liu, Liyuan Guo, Dennis Walter, Saif-Ur Rehman, Stefan Scholze, Sebastian Höppner, Christian Mayr
ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data. AICAS (2022)
Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Richard George, Florian Kelber, Heiner Bauer, Stefan Scholze, Stefan Hänzsche, Marco Stolba, Andreas Dixius, Georg Ellguth, Dennis Walter, Sebastian Höppner, Christian Mayr
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. IEEE Trans. Biomed. Circuits Syst. 16 (1) (2022)
Sebastian Höppner, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Marco Stolba, Florian Kelber, Bernhard Vogginger, Felix Neumärker, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Thomas Hocker, Dennis Walter, Gengting Liu, Jim D. Garside, Steve B. Furber, Christian Mayr
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. CoRR (2021)
Heiner Bauer, Sebastian Höppner, Chris Paul Iatrou, Zohra Charania, Stephan Hartmann, Saif-Ur Rehman, Andreas Dixius, Georg Ellguth, Dennis Walter, Johannes Uhlig, Felix Neumärker, Marc Berthel, Marco Stolba, Florian Kelber, Leon Urbas, Christian Mayr
Hardware Implementation of an OPC UA Server for Industrial Field Devices. CoRR (2021)
Heiner Bauer, Sebastian Höppner, Chris Paul Iatrou, Zohra Charania, Stephan Hartmann, Saif-Ur Rehman, Andreas Dixius, Georg Ellguth, Dennis Walter, Johannes Uhlig, Felix Neumärker, Marc Berthel, Marco Stolba, Florian Kelber, Leon Urbas, Christian Mayr
Hardware Implementation of an OPC UA Server for Industrial Field Devices. IEEE Trans. Very Large Scale Integr. Syst. 29 (11) (2021)
Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner
A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. COOL CHIPS (2020)
Sebastian Höppner, Holger Eisenreich, Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Jörg Schreiter, Thorsten Riedel, Heiner Bauer, Robert Niebsch, Stephan Scherzer, Thomas Hocker, Stefan Scholze, Stephan Henker, Matthias Nossmann, Ulrich Hensel, Helmut Prengel
Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Sebastian Höppner, Jörg Schreiter, Robert Niebsch, Stephan Scherzer, Ulrich Hensel, Jörg Winkler, Mario Orgis, Holger Eisenreich, Dennis Walter, Uwe Steeb, André Scharfe, Clifford Dmello, Robert Sinkwitz, Heiner Bauer, Alexander Oefelein, Florian Schraut
How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. ESSDERC (2019)
Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs. DATE (2018)
Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederström, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard P. Fettweis
A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. DAC (2017)
Heiner Bauer, Sebastian Höppner, Johannes Partzsch, Dennis Walter, Christian Mayr, Florian Schraut, Holger Eisenreich
Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. NORCAS (2017)
Michael Raitza, Akash Kumar, Marcus Völp, Dennis Walter, Jens Trommer, Thomas Mikolajick, Walter M. Weber
Exploiting transistor-level reconfiguration to optimize combinational circuits. DATE (2017)
Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis
An MPSoC for energy-efficient database query processing. DAC (2016)
Andreas Dixius, Dennis Walter, Sebastian Höppner, Holger Eisenreich, René Schüffny
A deep-submicron CMOS flow for general-purpose timing-detection insertion. MIXDES (2015)
Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schluessler, Holger Eisenreich, René Schüffny
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. IEEE J. Solid State Circuits 50 (3) (2015)
Johannes Gorner, Sebastian Höppner, Dennis Walter, Michael Haas, Dirk Plettemeier, René Schüffny
An energy efficient multi-bit TSV transmitter using capacitive coupling. ICECS (2014)
Benedikt Noethen, Oliver Arnold, Esther P. Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, J.-U. Schlusler, Stefan Scholze, Dennis Walter, René Schüffny
heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. ISSCC (2014)
Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny
A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Sebastian Höppner, Stefan Hänzsche, Georg Ellguth, Dennis Walter, Holger Eisenreich, René Schüffny
A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (11) (2013)
Sebastian Höppner, Dennis Walter, Holger Eisenreich, Stefan Schiefer, René Schüffny
Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology. ECCTD (2013)
Sebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny
On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links. Int. J. Embed. Real Time Commun. Syst. 3 (4) (2012)
Holger Täubig, Udo Frese, Christoph Hertzberg, Christoph Lüth, Stefan Mohr, Elena Vorobev, Dennis Walter
Guaranteeing functional safety: design for provability and computer-aided verification. Auton. Robots 32 (3) (2012)
Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter, Gerhard P. Fettweis
A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. ISSCC (2012)
Sebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny
Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. SoC (2011)
Sebastian Höppner, Dennis Walter, Holger Eisenreich, René Schüffny
Efficient compensation of delay variations in high-speed network-on-chip data links. SoC (2010)
Dennis Walter, Holger Täubig, Christoph Lüth
Experiences in Applying Formal Verification in Robotics. SAFECOMP (2010)
Christoph Lüth, Dennis Walter
Certifiable Specification and Verification of C Programs. FM (2009)
Udo Frese, Daniel Hausmann, Christoph Lüth, Holger Täubig, Dennis Walter
The Importance of Being Formal. Electron. Notes Theor. Comput. Sci. 238 (4) (2009)
Udo Frese, Daniel Hausmann, Christoph Lüth, Holger Täubig, Dennis Walter
Zertifizierung einer Sicherungskomponente mittels durchgängig formaler Modellierung. Software Engineering (Workshops) (2008)
Reiner Hähnle, Jing Pan, Philipp Rümmer, Dennis Walter
Integration of a security type system into a program logic. Theor. Comput. Sci. 402 (2-3) (2008)
Reiner Hähnle, Jing Pan, Philipp Rümmer, Dennis Walter
Integration of a Security Type System into a Program Logic. TGC (2006)
Dennis Walter, Lutz Schröder, Till Mossakowski
Parametrized Exceptions. CALCO (2005)

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Publication Activity (10 Years)

Top Topics

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Dennis Walter