Seyed Mohammad Ali Zeinolabedin

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 21

Top Topics

Laplacian Pyramid

Keyword Spotting

Adaptive Neural

Data Compression

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Franz Marcus Schüffny, Stefan Hänzsche, Stephan Henker, Seyed Mohammad Ali Zeinolabedin, Stefan Scholze, Sebastian Höppner, Richard Miru George, Christian Mayr
A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI. NEWCAS (2023)
Liyuan Guo, Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Annika Weiße, Stefan Scholze, Richard George, Johannes Partzsch, Christian Mayr
A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI. NEWCAS (2023)
Liyuan Guo, Matthias Jobst, Johannes Partzsch, Stefan Scholze, Andreas Dixius, Matthias Lohrmann, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI. AICAS (2023)
Franz Marcus Schüffny, Sebastian Höppner, Seyed Mohammad Ali Zeinolabedin, Richard Miru George, Christian Mayr
How to design an input stage for neural recording system in 22 nm FDSOI. PRIME (2022)
Franz Marcus Schüffny, Stefan Hänzsche, Marc Berthel, Seyed Mohammad Ali Zeinolabedin, Stefan Scholze, Sebastian Höppner, Richard Miru George, Christian Mayr
A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm. NorCAS (2022)
Franz Marcus Schüffny, Sebastian Höppner, Stefan Hänzsche, Richard Miru George, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Richard George, Florian Kelber, Heiner Bauer, Stefan Scholze, Stefan Hänzsche, Marco Stolba, Andreas Dixius, Georg Ellguth, Dennis Walter, Sebastian Höppner, Christian Mayr
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. IEEE Trans. Biomed. Circuits Syst. 16 (1) (2022)
Shengpeng Guo, Liyuan Guo, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
Various Distance Metrics Evaluation on Neural Spike Classification. BioCAS (2022)
Qier Ma, Liyuan Guo, Seyed Mohammad Ali Zeinolabedin, Christian Mayr
Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression. BioCAS (2021)
Seyed Mohammad Ali Zeinolabedin, Johannes Partzsch, Christian Mayr
Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator. DATE (2021)
Seyed Mohammad Ali Zeinolabedin, Johannes Partzsch, Christian Mayr
Real-time Hardware Implementation of ARM CoreSight Trace Decoder. IEEE Des. Test 38 (1) (2021)
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Tony Tae-Hyoung Kim
A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2016)
Seyed Mohammad Ali Zeinolabedin, Nader Karimi, Shadrokh Samavi, Tony Tae-Hyoung Kim
Structuring of Contourlet Transform for Pipeline-Based Implementation. Circuits Syst. Signal Process. 35 (3) (2016)
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications. A-SSCC (2016)
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
per channel in 65-nm CMOS. VLSI Circuits (2016)
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
per Channel in 65-nm CMOS. APCCAS (2016)
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony T. Kim
A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression. ESSCIRC (2015)
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony Tae-Hyoung Kim
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. ISCAS (2015)
Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony T. Kim
An area- and power-efficient FIFO with error-reduced data compression for image/video processing. ISCAS (2014)