Anh-Tuan Do

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 22

Top Topics

Detection Algorithm

Energy Efficiency

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Quang-Manh Duong, Khoa-Sang Nguyen, Hai-Duong Nguyen, Xuan-Uoc Dao, Anh-Tuan Do, Quang-Kien Trinh
FeCBF: A Novel Sub-Optimal Cascaded Bloom Filter Structure Based on Feature Extraction. IEEE Access 12 (2024)
Lu Lu, Anh-Tuan Do
A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Yi Sheng Chong, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, K. T. C. Chai, Anh-Tuan Do
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSCIRC (2021)
Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, K. T. C. Chai, Anh-Tuan Do
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSDERC (2021)
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Bin Zhao, Yi Sheng Chong, Anh-Tuan Do
Area and Energy Efficient 2D Max-Pooling For Convolutional Neural Network Hardware Accelerator. IECON (2020)
Zhehui Wang, Huaipeng Zhang, Tao Luo, Weng-Fai Wong, Anh-Tuan Do, Paramasivam Vishnu, Wei Zhang, Rick Siow Mong Goh
NCPower: Power Modelling for NVM-based Neuromorphic Chip. ICONS (2020)
Kian Ann Ng, Chao Yuan, Astrid Rusly, Anh-Tuan Do, Bin Zhao, Shih-Chiang Liu, Wendy Yen Xian Peh, Thow Xin Yuan, Kai Voges, Sanghoon Lee, Gil Gerald Lasam Gammad, Khay-Wai Leong, John S. Ho, Silvia Bossi, Gemma Taverni, Annarita Cutrone, Shih-Cheng Yen, Yong Ping Xu
A Wireless Multi-Channel Peripheral Nerve Signal Acquisition System-on-Chip. IEEE J. Solid State Circuits 54 (8) (2019)
Junran Pu, Vishnu P. Nambiar, Anh-Tuan Do, Wang Ling Goh
Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm. ISCAS (2019)
Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers. SoCC (2019)
Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. SoCC (2019)
Anh-Tuan Do
0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique. SoCC (2019)
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Ming Ming Wong, Anh-Tuan Do
Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function. SoCC (2019)
Fei Li, Ming Ming Wong, Aarthy Mani, Vishnu Paramasivam, Anh-Tuan Do
0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications. A-SSCC (2019)
Anh-Tuan Do, Xin Liu
25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme. A-SSCC (2017)
Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Xin Liu, Tony Tae-Hyoung Kim
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization. IEEE J. Solid State Circuits 51 (6) (2016)
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications. A-SSCC (2016)
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
per channel in 65-nm CMOS. VLSI Circuits (2016)
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
per Channel in 65-nm CMOS. APCCAS (2016)
Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim
A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation. ISCAS (2015)
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. ISCAS (2015)
Bo Wang, Truc Quynh Nguyen, Anh-Tuan Do, Jun Zhou, Minkyu Je, Tony Tae-Hyoung Kim
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Anh-Tuan Do, Chun Yin, Kavitha Velayudhan, Zhao Chuan Lee, Kiat Seng Yeo, Tony Tae-Hyoung Kim
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance. IEEE J. Solid State Circuits 49 (7) (2014)
Kiat Seng Yeo, Mojy Curtis Chian, Tony Chon Wee Ng, Anh-Tuan Do
Internet of Things: Trends, challenges and applications. ISIC (2014)
Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Tony Tae-Hyoung Kim
0.2 V 8T SRAM with improved bitline sensing using column-based data randomization. A-SSCC (2014)
Anh-Tuan Do, Kiat Seng Yeo
A hybrid NEO-based spike detection algorithm for implantable brain-IC interface applications. ISCAS (2014)
Anh-Tuan Do, Karthik G. Jayaraman, Pushpapraj Singh, Chua Geng Li, Kiat Seng Yeo, Tony Tae-Hyoung Kim
Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset. ESSDERC (2013)
Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Anh-Tuan Do, Yung Sern Tan, Gordon M. Xiong, Cleo Choong, Zhi-Hui Kong, Kiat Seng Yeo
A current-mode stimulator circuit with two-step charge balancing background calibration. ISCAS (2013)
Anh-Tuan Do, Karthik G. Jayaraman, Vincent Pott, Chua Geng Li, Pushpapraj Singh, Kiat Seng Yeo, Tony Tae-Hyoung Kim
An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory. ISCAS (2013)
Anh-Tuan Do, Truc Quynh Nguyen, Kiat Seng Yeo, Tony Tae-Hyoung Kim
Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Anh-Tuan Do, Yung Sern Tan, Chun Kit Lam, Minkyu Je, Kiat Seng Yeo
Low power implantable neural recording front-end. ISOCC (2012)
Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Lei Yao, Meng Tong Tan, Minkyu Je
A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems. APCCAS (2012)
Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Xiaodan Zou, Lei Yao, Kuang-Wei Cheng, Minkyu Je
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. NEWCAS (2012)
Vikas Chandan, Anh-Tuan Do, Baoduo Jin, Faryar Jabbari, Jack Brouwer, Ioannis Akrotirianakis, Amit Chakraborty, Andrew G. Alleyne
Modeling and optimization of a combined cooling, heating and power plant system. ACC (2012)
Tony T. Kim, Bo Wang, Anh-Tuan Do
High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture. ISOCC (2012)
Haitao Wang, Kiat Seng Yeo, Anh-Tuan Do, Yung Sern Tan, Kai Kang, Zhenghao Lu
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor. ISOCC (2012)
Xiaoliang Tan, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo, Zhi-Hui Kong
A new match line sensing technique in Content Addressable Memory. COOL Chips (2011)
Myat Thu Linn Aung, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo
Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor. VLSI-SoC (2011)
Anh-Tuan Do, Xiaoliang Tan, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs. ACM Great Lakes Symposium on VLSI (2011)
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
A low-power CAM with efficient power and delay trade-off. ISCAS (2011)
Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Zhi-Hui Kong, Anh-Tuan Do
A 16Kb 10T-SRAM with 4x read-power reduction. ISCAS (2010)
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo
Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2010)
Anh-Tuan Do, Kiat Seng Yeo, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. APCCAS (2010)
Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
Low IR drop and low power parallel CAM design using gated power transistor technique. APCCAS (2010)
Anh-Tuan Do, Jeremy Yung Shern Low, Zhi-Hui Kong, Kiat Seng Yeo, Joshua Yung Low Yung Lih
A full current-mode sense amplifier for low-power SRAM applications. APCCAS (2008)
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo
Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing. IEEE Trans. Circuits Syst. II Express Briefs (10) (2008)