An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS.
Anh-Tuan DoJeremy Yung Shern LowJoshua Yung Lih LowZhi-Hui KongXiaoliang TanKiat Seng YeoPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2011)
Keyphrases
- random access memory
- power consumption
- nm technology
- cmos technology
- low power
- design considerations
- low voltage
- noise level
- flip flops
- random noise
- embedded dram
- noise reduction
- data transmission
- silicon on insulator
- power reduction
- gaussian noise
- missing data
- high speed
- color images
- learning algorithm
- real time
- signal to noise ratio
- low cost
- leakage current
- training set
- image processing