Jeremy Yung Shern Low

Publication Activity (10 Years)

Years Active: 2008-2016
Publications (10 Years): 1

Top Topics

Vlsi Implementation

Digital Circuits

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
+1}". IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Jeremy Yung Shern Low, Chip-Hong Chang
A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2013)
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$. IEEE Trans. Very Large Scale Integr. Syst. 21 (10) (2013)
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
+1} RNS. ISCAS (2013)
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
+1} RNS scaler with dual scaling constants. APCCAS (2012)
Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. ISCAS (2012)
Jeremy Yung Shern Low, Chip-Hong Chang
+1 RNS. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2012)
Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS (2012)
Chip-Hong Chang, Jeremy Yung Shern Low
+ 1. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2011)
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
Jeremy Yung Shern Low, Chip-Hong Chang
+ 1}. ISCAS (2011)
Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang, Jeremy Yung Shern Low
A novel counter-based low complexity inner-product architecture for high speed inputs. ISCAS (2010)
Anh-Tuan Do, Kiat Seng Yeo, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. APCCAS (2010)
Anh-Tuan Do, Jeremy Yung Shern Low, Zhi-Hui Kong, Kiat Seng Yeo, Joshua Yung Low Yung Lih
A full current-mode sense amplifier for low-power SRAM applications. APCCAS (2008)