Thian Fatt Tay

Publication Activity (10 Years)

Years Active: 2012-2017
Publications (10 Years): 5

Top Topics

Modular Structure

Error Correction

Riemannian Manifolds

Vlsi Implementation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Sachin Kumar, Chip-Hong Chang, Thian Fatt Tay
-1} and Its Efficient Hardware Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2017)
Thian Fatt Tay, Chip-Hong Chang
A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS. IEEE Trans. Computers 65 (2) (2016)
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
+1}". IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Thian Fatt Tay, Chip-Hong Chang, Leonel Sousa
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2015)
Thian Fatt Tay, Chip-Hong Chang
A new unified modular adder/subtractor for arbitrary moduli. ISCAS (2015)
Thian Fatt Tay, Chip-Hong Chang
A new algorithm for single residue digit error correction in Redundant Residue Number System. ISCAS (2014)
Thian Fatt Tay, Chip-Hong Chang
-1}. APCCAS (2014)
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$. IEEE Trans. Very Large Scale Integr. Syst. 21 (10) (2013)
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
+1} RNS. ISCAS (2013)
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
+1} RNS scaler with dual scaling constants. APCCAS (2012)
Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. ISCAS (2012)