Ching-Chuen Jong

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 4

Top Topics

Image Filtering

Discrete Wavelet Transform

Top Venues

IEEE Trans. Computers

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Lei Wu, Ching-Chuen Jong
Non-iterative division circuit design with accuracy and performance trade-off based on mixed integer linear programming approach. Microelectron. J. 127 (2022)
Lei Wu, Ching-Chuen Jong
A High-Throughput VLSI Architecture for Real-Time Full-HD Gradient Guided Image Filter. IEEE Trans. Circuits Syst. Video Technol. 29 (6) (2019)
Joshua Yung Lih Low, Ching-Chuen Jong
Range Mapping - A Fresh Approach to High Accuracy Mitchell-Based Logarithmic Conversion Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Lei Wu, Ching-Chuen Jong
A VLSI architecture for real-time gradient guided image filtering. VLSI-SoC (2016)
Yusong Hu, Ching-Chuen Jong
Memory-efficient discrete wavelet transform architecture based on wordlength optimization. ISCAS (2015)
Joshua Yung Lih Low, Ching-Chuen Jong
Unified Mitchell-Based Approximation for Efficient Logarithmic Conversion Circuit. IEEE Trans. Computers 64 (6) (2015)
Lei Wu, Ching-Chuen Jong
A curve fitting approach for non-iterative divider design with accuracy and performance trade-off. NEWCAS (2015)
Yusong Hu, Ching-Chuen Jong
A Memory-Efficient High-Throughput Architecture for Lifting-Based Multi-Level 2-D DWT. IEEE Trans. Signal Process. 61 (20) (2013)
Joshua Yung Lih Low, Ching-Chuen Jong
Non-iterative high speed division computation based on Mitchell logarithmic method. ISCAS (2013)
Yusong Hu, Ching-Chuen Jong
A Memory-Efficient Scalable Architecture for Lifting-Based Discrete Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs (8) (2013)
Joshua Yung Lih Low, Ching-Chuen Jong
A Memory-Efficient Tables-and-Additions Method for Accurate Computation of Elementary Functions. IEEE Trans. Computers 62 (5) (2013)
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang
An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2012)
J. W. Luo, Ching-Chuen Jong
Scalable linear array architectures for matrix inversion using Bi-z CORDIC. Microelectron. J. 43 (2) (2012)
Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. ISCAS (2012)
Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS (2012)
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters. IEEE Trans. Very Large Scale Integr. Syst. 19 (10) (2011)
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang, Jeremy Yung Shern Low
A novel counter-based low complexity inner-product architecture for high speed inputs. ISCAS (2010)
Joshua Yung Lih Low, Ching-Chuen Jong
High accuracy binary logarithmic conversion using range mapping for DSP applications. APCCAS (2010)
Jiajia Chen, Chip-Hong Chang, Ching-Chuen Jong
Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block. ISCAS (2009)
Xianwu Xing, Ching-Chuen Jong
Floorplan-Driven Multivoltage High-Level Synthesis. VLSI Design 2009 (2009)
Xianwu Xing, Ching-Chuen Jong
Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2008)
Ramya Muralidharan, Chip-Hong Chang, Ching-Chuen Jong
+1 squarer design. APCCAS (2008)
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang
High-speed and low-power serial accumulator for serial/parallel multiplier. APCCAS (2008)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (10) (2007)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
Hamming weight pyramid - A new insight into canonical signed digit representation and its applications. Comput. Electr. Eng. 33 (3) (2007)
Xianwu Xing, Ching-Chuen Jong
A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis. Microelectron. J. 38 (4-5) (2007)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
A new integrated approach to the design of low-complexity FIR filters. ISCAS (2006)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
Contention resolution algorithm for common subexpression elimination in digital filter design. IEEE Trans. Circuits Syst. II Express Briefs (10) (2005)
Xianwu Xing, Ching-Chuen Jong
Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis. ISCAS (6) (2005)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. ISCAS (2) (2005)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
HWP: a new insight into canonical signed digit. ISCAS (5) (2004)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. ISCAS (3) (2004)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
Efficient algorithms for common subexpression elimination in digital filter design. ICASSP (5) (2004)
Zhaoxuan Shen, Ching-Chuen Jong
Functional area lower bound and upper bound on multicomponentselection for interval scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (7) (2000)
Z. X. Shen, Ching-Chuen Jong
A lower bound on general minimal resource interval scheduling with arbitrary component selection. ISCAS (6) (1999)
Ching-Chuen Jong, Y. Y. H. Lam, L. S. Ng
FPGA implementation of a digital IQ demodulator using VHDL. FPL (1997)
Ching-Chuen Jong, Y. Y. H. Lam, S. S. Lim, T. S. Teng
Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. ISCAS (1994)