ISCAS (6)

Keyphrases

Publications

2005

M. Ma, E. Masoud, Y. Sun, John M. Senior
A hybrid space-time and collaborative coding scheme for wireless communications. ISCAS (6) (2005)
Kalle Folkesson, Christer Svensson, B. Knuthammar, A. Dreyfert
A high-level dynamic-error model of a pipelined analog-to-digital converter. ISCAS (6) (2005)
Ge Yang, Yong Sin Kim, Sung-Mo Kang
Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications. ISCAS (6) (2005)
Holly Pekau, Lee Hartley, James W. Haslett
A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications]. ISCAS (6) (2005)
Walter D. Leon-Salas, Sina Balkir, Khalid Sayood, Michael W. Hoffman
An analog-to-digital converter with Golomb-Rice output codes. ISCAS (6) (2005)
Mohammad Yavari, Omid Shoaei
High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications. ISCAS (6) (2005)
Muhammad Shakeel Qureshi, Phillip E. Allen
70 MHz CMOS gm-C IF filter. ISCAS (6) (2005)
Tsung-Hsi Chiang, Lan-Rong Dung, Ming-Feng Yaung
Modeling and formal verification of dataflow graph in system-level design using Petri net. ISCAS (6) (2005)
Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
A 0.35µm CMOS comparator circuit for high-speed ADC applications. ISCAS (6) (2005)
Wenxian Yang, Feng Wu, Yan Lu, Jianfei Cai, King Ngi Ngan, Shipeng Li
Scalable multiview video coding using wavelet. ISCAS (6) (2005)
Yu-Wen Huang, Chia-Lin Lee, Ching-Yeh Chen, Liang-Gee Chen
One-pass computation-aware motion estimation with adaptive search strategy. ISCAS (6) (2005)
Li-Fu Ding, Shao-Yi Chien, Yu-Wen Huang, Yu-Lin Chang, Liang-Gee Chen
Stereo video coding system with hybrid coding based on joint prediction scheme. ISCAS (6) (2005)
Paolo Arena, Luigi Fortuna, Mattia Frasca, Guido Vagliasindi, Adriano Basile
CNN wave based computation for robot navigation on ACE16K. ISCAS (6) (2005)
Yun Ye, Saman S. Abeysekera
Evaluating a blind channel estimation technique that uses a hardware efficient equalizer. ISCAS (6) (2005)
Martijn F. Snoeij, Albert J. P. Theuwissen, Johan H. Huijsing
A 1.8 V 3.2µW comparator for use in a CMOS imager column-level single-slope ADC. ISCAS (6) (2005)
Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang, Hsin-Hsien Ho
Modem floorplanning with abutment and fixed-outline constraints. ISCAS (6) (2005)
Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma
A multiplication-accumulation computation unit with optimized compressors and minimized switching activities. ISCAS (6) (2005)
Yiwen Zhang, Qinye Yin, Le Ding, Ronghai Sun
Blind low rate multiuser detection for multirate multicarrier CDMA systems using antenna array. ISCAS (6) (2005)
You Zheng, Carlos E. Saavedra
A BPSK demodulator circuit using an anti-parallel synchronization loop. ISCAS (6) (2005)
Ákos Zarándy, Péter Földesy, Péter Szolgay, Szabolcs Tõkés, Csaba Rekeczky, Tamás Roska
Various implementations of topographic, sensory, cellular wave computers. ISCAS (6) (2005)
Vivek Sharma, Un-Ku Moon, Gabor C. Temes
A generic multilevel multiplying D/A converter for pipelined ADCs. ISCAS (6) (2005)
Takayuki Watanabe, Hideki Asai
Modeling of power distribution networks with signal lines for SPICE simulators. ISCAS (6) (2005)
Guoping Qiu, Jiang Duan
An optimal tone reproduction curve operator for the display of high dynamic range images. ISCAS (6) (2005)
Shigeki Tsuji, Tetsushi Ueta, Hiroshi Kawakami, Kazuyuki Aihara
Bifurcations in modified BVP neurons connected by inhibitory and electrical coupling. ISCAS (6) (2005)
Yin-Tsung Hwang, Chen-Yu Tsai, Cheng-Chen Lin
Block-wise adaptive modulation for OFDM WLAN systems. ISCAS (6) (2005)
Hsiang-Feng Chi, Zhao-Hong Lai
A cost-effective memory-based real-valued FFT and Hermitian symmetric IFFT processor for DMT-based wire-line transmission systems. ISCAS (6) (2005)
Dinh Hung Dang, Yvon Savaria, Mohamad Sawan
A novel approach for implementing ultra-high speed flash ADC using MCML circuits. ISCAS (6) (2005)
Augusto Santiago Cerqueira, Carlos Augusto Duque, Rogério Marques Trindade, Moisés Vidal Ribeiro
Digital system for detection and classification of electrical events. ISCAS (6) (2005)
Slawomir Koziel, John W. Bandler, Kaj Madsen
Towards a rigorous formulation of the space mapping technique for engineering design. ISCAS (6) (2005)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) (2005)
Oguz Altun, Jinseok Koh, Phillip E. Allen
A 1.5V multirate multibit sigma delta modulator for GSM/WCDMA in a 90 nm digital CMOS process. ISCAS (6) (2005)
Pieter Harpe, Athon Zanikopoulos, Arthur H. M. van Roermund
Digital self-correction of time-interleaved ADCs. ISCAS (6) (2005)
Fabian J. Theis
Blind signal separation into groups of dependent signals using joint block diagonalization. ISCAS (6) (2005)
In-Cheol Park, Se-Hyeon Kang
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. ISCAS (6) (2005)
Tuna B. Tarim
Mixed signal and SoC design flow requirements. ISCAS (6) (2005)
Piotr Dudek
Implementation of SIMD vision chip with 128×128 array of analogue processing elements. ISCAS (6) (2005)
Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla
Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters. ISCAS (6) (2005)
Massimo Panella, Maurizio Paschero, Fabio Massimo Frattale Mascioli
A modular RC-active network for vibration damping in piezo-electro-mechanical beams. ISCAS (6) (2005)
Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero
Linear and nonlinear macromodels for power/signal integrity. ISCAS (6) (2005)
Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg
A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch. ISCAS (6) (2005)
Li Guo, Yih-Fang Huang
SMF robust filtering in impulsive noise. ISCAS (6) (2005)
Dahua Xie, C.-C. Jay Kuo
Multimedia data encryption via random rotation in partitioned bit streams. ISCAS (6) (2005)
Philomena C. Brady, Paul E. Hasler
Offset compensation in flash ADCs using floating-gate circuits. ISCAS (6) (2005)
Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma
Reconfigurable multiple scan-chains for reducing test application time of SOCs. ISCAS (6) (2005)
Müstak E. Yalçin, Johan A. K. Suykens, Joos Vandewalle
Spatiotemporal pattern formation in the ACE16k CNN chip. ISCAS (6) (2005)
Yue Ma, Hiroshi Kawakami, Chi K. Michael Tse, Takuji Kousaka
A subtle link in switched dynamical systems: saddle-node bifurcation meets border collision. ISCAS (6) (2005)
Jan H. Rutger Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta
Jitter limitations on multi-carrier modulation. ISCAS (6) (2005)
Chun Luo, Jun Yang, Gugang Gao, Longxing Shi
Domain fault model and coverage metric for SoC verification. ISCAS (6) (2005)
Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang
FPGA technology mapping optimization by rewiring algorithms. ISCAS (6) (2005)
Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. ISCAS (6) (2005)