Joshua Yung Lih Low

Publication Activity (10 Years)

Years Active: 2010-2018
Publications (10 Years): 2

Top Topics

Computationally Efficient

Top Venues

IEEE Trans. Computers

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Joshua Yung Lih Low, Ching-Chuen Jong
Range Mapping - A Fresh Approach to High Accuracy Mitchell-Based Logarithmic Conversion Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Joshua Yung Lih Low, Ching-Chuen Jong
Unified Mitchell-Based Approximation for Efficient Logarithmic Conversion Circuit. IEEE Trans. Computers 64 (6) (2015)
Joshua Yung Lih Low, Ching-Chuen Jong
Non-iterative high speed division computation based on Mitchell logarithmic method. ISCAS (2013)
Joshua Yung Lih Low, Ching-Chuen Jong
A Memory-Efficient Tables-and-Additions Method for Accurate Computation of Elementary Functions. IEEE Trans. Computers 62 (5) (2013)
Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. ISCAS (2012)
Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS (2012)
Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Joshua Yung Lih Low, Ching-Chuen Jong
High accuracy binary logarithmic conversion using range mapping for DSP applications. APCCAS (2010)
Anh-Tuan Do, Kiat Seng Yeo, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. APCCAS (2010)