Vishnu P. Nambiar

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 23

Top Topics

Quality Assessment

Routing Algorithm

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Zhangyi Pei, Vishnu P. Nambiar, Yi Sheng Chong, Wang Ling Goh, Anh Tuan Do
3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications. ISCAS (2024)
Yi Sheng Chong, Rakshith Harish, Rajesh Chandrasekhara Panicker, Vishnu P. Nambiar, Anh Tuan Do
A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation. ISCAS (2024)
Yi Sheng Chong, Hongyu Cao, Wang Ling Goh, Patrick Bore, Yuanzheng Paul Tan, Yung Szen Yap, Rainer Dumke, Vishnu P. Nambiar, Anh Tuan Do
Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature. ISCAS (2024)
Nazim Altar Koca, Chip-Hong Chang, Anh Tuan Do, Vishnu P. Nambiar
Exploring Error Correction Circuits on RISC-V based Systems for Space Applications. ISCAS (2024)
Yi Sheng Chong, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training. ISCAS (2022)
Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications. ISCAS (2022)
Jingjing Lan, Vishnu P. Nambiar, Ming Ming Wong, Fei Li, Yuan Gao, Kevin Tshun Chuan Chai, Anh Tuan Do
, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS. ISCAS (2022)
Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
Efficient Implementation of Activation Functions for LSTM accelerators. VLSI-SoC (2021)
Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Ming Ming Wong, Anh Tuan Do
A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (12) (2021)
Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, K. T. C. Chai, Anh-Tuan Do
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSCIRC (2021)
Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Yi Sheng Chong, Anh Tuan Do
A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do
An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks. ISCAS (2021)
Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do
Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, K. T. C. Chai, Anh-Tuan Do
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSDERC (2021)
Yun Kwan Lee, Vishnu P. Nambiar, Kim Seng Goh, Anh Tuan Do
Post-Silicon Validation Methodology for Resource-Constrained Neuromorphic Hardware. IECON (2020)
Vishnu P. Nambiar, Eng-Kiat Koh, Junran Pu, Aarthy Mani, Ming Ming Wong, Li Fei, Wang Ling Goh, Anh Tuan Do
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model. ISCAS (2020)
Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, T. Luo, L. Yang, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do
0.5V 4.8 pJ/SOP 0.93\mu \mathrm{W}$ Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. A-SSCC (2020)
Junran Pu, Vishnu P. Nambiar, Anh-Tuan Do, Wang Ling Goh
Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm. ISCAS (2019)
Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers. SoCC (2019)
Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing. SoCC (2019)
Yee Hui Lee, Mohamed Khalil Hani, Rabia Bakhteri, Vishnu P. Nambiar
A real-time near infrared image acquisition system based on image quality assessment. J. Real Time Image Process. 13 (1) (2017)
Vishnu P. Nambiar, Mohamed Khalil Hani, Riadh Sahnoun, Muhammad N. Marsono
Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function. Neurocomputing 140 (2014)
Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad N. Marsono, Chen Wei Sia
Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm. Neurocomputing 145 (2014)
Vishnu P. Nambiar, Sathivellu Balakrishnan, Mohamed Khalil Hani, Muhammad N. Marsono
HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems. Computing 95 (9) (2013)
Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono
Co-simulation methodology for improved design and verification of hardware neural networks. IECON (2013)
Mohamed Khalil Hani, Vishnu P. Nambiar, Muhammad N. Marsono
GA-based parameter tuning in finger-vein biometric embedded systems for information security. ICCC (2012)
Vishnu P. Nambiar, Mohamed Khalil Hani, Muhammad Munim Ahmad Zabidi
Accelerating the AES encryption function in OpenSSL for embedded systems. Int. J. Inf. Commun. Technol. 2 (1/2) (2009)