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Lu Lu
ORCID
Publication Activity (10 Years)
Years Active: 2018-2024
Publications (10 Years): 20
Top Topics
Low Power
Memory Requirements
Artificial Intelligence
Portable Devices
Top Venues
ISCAS
IEEE Trans. Circuits Syst. II Express Briefs
A-SSCC
IEEE Trans. Circuits Syst. I Regul. Pap.
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Publications
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Junjie Mu
,
Lu Lu
,
Ju Eon Kim
,
Byung-Kwon An
,
Vishal Sharma
,
Arya Jagath Lekshmi
,
Putu Andhita Dananjaya
,
Weng Hong Lai
,
Wen Siang Lew
,
Tony Tae-Hyoung Kim
A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation.
IEEE Trans. Circuits Syst. II Express Briefs
71 (5) (2024)
Qibang Zang
,
Wang Ling Goh
,
Lu Lu
,
Chengshuo Yu
,
Junjie Mu
,
Tony Tae-Hyoung Kim
,
Bongjin Kim
,
Dongrui Lit
,
Anh Tuan Do
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
ISCAS
(2023)
Lu Lu
,
Aarthy Mani
,
Anh Tuan Do
A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips.
ISCAS
(2023)
Lu Lu
,
Anh-Tuan Do
A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications.
IEEE Trans. Circuits Syst. II Express Briefs
70 (9) (2023)
Yuzong Chen
,
Junjie Mu
,
Hyunjoon Kim
,
Lu Lu
,
Tony Tae-Hyoung Kim
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
70 (5) (2023)
Lu Lu
,
Taegeun Yoo
,
Tony Tae-Hyoung Kim
A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
69 (6) (2022)
Yuzong Chen
,
Junjie Mu
,
Hyunjoon Kim
,
Lu Lu
,
Tony Tae-Hyoung Kim
A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
ISCAS
(2022)
Lu Lu
,
Tony Tae-Hyoung Kim
A High Reliable SRAM-Based PUF With Enhanced Challenge-Response Space.
IEEE Trans. Circuits Syst. II Express Briefs
69 (2) (2022)
Vishal Sharma
,
Ju Eon Kim
,
Hyunjoon Kim
,
Lu Lu
,
Tony Tae-Hyoung Kim
A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst.
12 (2) (2022)
Yuzong Chen
,
Lu Lu
,
Yuncheng Lu
,
Tony Tae-Hyoung Kim
A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory.
ISCAS
(2021)
Yuzong Chen
,
Lu Lu
,
Bongjin Kim
,
Tony Tae-Hyoung Kim
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.
IEEE Open J. Circuits Syst.
2 (2021)
Lu Lu
,
Yu Zong Chen
,
Tony Tae-Hyoung Kim
A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme.
ISCAS
(2021)
Lu Lu
,
Tony Tae-Hyoung Kim
A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking.
A-SSCC
(2021)
Yuzong Chen
,
Lu Lu
,
Bongjin Kim
,
Tony Tae-Hyoung Kim
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst.
28 (12) (2020)
Yuzong Chen
,
Lu Lu
,
Bongjin Kim
,
Tony Tae-Hyoung Kim
Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
ISCAS
(2020)
Lu Lu
,
Ju Eon Kim
,
Vishal Sharma
,
Tony Tae-Hyoung Kim
ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology.
APCCAS
(2020)
Lu Lu
,
Taegeun Yoo
,
Van Loi Le
,
Tony Tae-Hyoung Kim
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines.
IEEE Trans. Very Large Scale Integr. Syst.
28 (6) (2020)
Lu Lu
,
Tony Tae-Hyoung Kim
A Sequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space.
ISCAS
(2019)
Achiranshu Garg
,
Zhao Chuan Lee
,
Lu Lu
,
Tony Tae-Hyoung Kim
Improving uniformity and reliability of SRAM PUFs utilizing device aging phenomenon for unique identifier generation.
Microelectron. J.
90 (2019)
Lu Lu
,
Taegeun Yoo
,
Van Loi Le
,
Tony Tae-Hyoung Kim
An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist.
A-SSCC
(2018)