A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation.

Anh-Tuan Do Kiat Seng Yeo Tony Tae-Hyoung Kim

Published in: ISCAS (2015)

Keyphrases

low voltage
random access memory
power line
leakage current
high speed
design considerations
cmos technology
knowledge base
real time
power management
image processing
power consumption
data transmission
motion segmentation