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A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology.
Sebastian Höppner
Stefan Hänzsche
Georg Ellguth
Dennis Walter
Holger Eisenreich
René Schüffny
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2013)
Keyphrases
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cmos technology
low power
user friendly
power consumption
low voltage
spl times
parallel processing
power dissipation
low cost
high speed
mixed signal
silicon on insulator
image sensor
phase locked loop
computer vision and image processing